Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	93.75	100.00	75.00			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	95.31	100.00	81.25			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.89			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T12,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T12,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T110
1	1	0	Not Covered
1	1	1	Covered	T9,T12,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T111,T112,T113
1	0	1	Covered	T9,T12,T10
1	1	0	Not Covered
1	1	1	Covered	T9,T12,T10

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T9,T12,T10
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T9,T12,T10

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T12,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	444193472	977430	0	0
DepthKnown_A	444534064	444221592	0	0
RvalidKnown_A	444534064	444221592	0	0
WreadyKnown_A	444534064	444221592	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	444534064	1074139	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444193472	977430	0	0
T4	294	0	0	0
T5	756	0	0	0
T9	8620	4198	0	0
T10	0	3232	0	0
T11	0	2393	0	0
T12	6008	1480	0	0
T17	4004	0	0	0
T18	3826	0	0	0
T19	0	1034	0	0
T26	5106	0	0	0
T27	2914	0	0	0
T31	0	4185	0	0
T43	2384	0	0	0
T48	0	866	0	0
T59	0	8861	0	0
T109	2204	0	0	0
T114	0	3077	0	0
T115	0	1674	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444534064	444221592	0	0
T1	4190	4086	0	0
T2	10726	10558	0	0
T3	33500	18560	0	0
T4	728	478	0	0
T9	8620	8434	0	0
T12	6008	5880	0	0
T17	4004	3856	0	0
T22	3630	3476	0	0
T26	5106	4984	0	0
T27	2914	2780	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444534064	444221592	0	0
T1	4190	4086	0	0
T2	10726	10558	0	0
T3	33500	18560	0	0
T4	728	478	0	0
T9	8620	8434	0	0
T12	6008	5880	0	0
T17	4004	3856	0	0
T22	3630	3476	0	0
T26	5106	4984	0	0
T27	2914	2780	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	444534064	444221592	0	0
T1	4190	4086	0	0
T2	10726	10558	0	0
T3	33500	18560	0	0
T4	728	478	0	0
T9	8620	8434	0	0
T12	6008	5880	0	0
T17	4004	3856	0	0
T22	3630	3476	0	0
T26	5106	4984	0	0
T27	2914	2780	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	444534064	1074139	0	0
T4	728	0	0	0
T5	3926	0	0	0
T9	8620	4198	0	0
T10	0	3232	0	0
T11	0	2393	0	0
T12	6008	1480	0	0
T16	0	366	0	0
T17	4004	0	0	0
T18	3826	0	0	0
T19	0	1034	0	0
T26	5106	0	0	0
T27	2914	0	0	0
T31	0	4185	0	0
T43	2384	0	0	0
T59	0	8861	0	0
T109	2204	0	0	0
T114	0	3077	0	0
T115	0	1674	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T12,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T12,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T9,T12,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T111,T112,T113
1	0	1	Covered	T9,T12,T10
1	1	0	Not Covered
1	1	1	Covered	T9,T12,T10

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T9,T12,T10
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T9,T12,T10

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T12,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	222096736	493470	0	0
DepthKnown_A	222267032	222110796	0	0
RvalidKnown_A	222267032	222110796	0	0
WreadyKnown_A	222267032	222110796	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	222267032	542190	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222096736	493470	0	0
T4	147	0	0	0
T5	378	0	0	0
T9	4310	2112	0	0
T10	0	1631	0	0
T11	0	1202	0	0
T12	3004	776	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T19	0	559	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T31	0	2166	0	0
T43	1192	0	0	0
T48	0	422	0	0
T59	0	4431	0	0
T109	1102	0	0	0
T114	0	1597	0	0
T115	0	891	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	222110796	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	364	239	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	222110796	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	364	239	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	222110796	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	364	239	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	542190	0	0
T4	364	0	0	0
T5	1963	0	0	0
T9	4310	2112	0	0
T10	0	1631	0	0
T11	0	1202	0	0
T12	3004	776	0	0
T16	0	182	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T19	0	559	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T31	0	2166	0	0
T43	1192	0	0	0
T59	0	4431	0	0
T109	1102	0	0	0
T114	0	1597	0	0
T115	0	891	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T116,T7,T117
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T12,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T110
1	1	0	Not Covered
1	1	1	Covered	T9,T12,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T118,T119,T120
1	0	1	Covered	T9,T12,T10
1	1	0	Not Covered
1	1	1	Covered	T9,T12,T10

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T9,T12,T10
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T9,T12,T10

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T12,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	222096736	483960	0	0
DepthKnown_A	222267032	222110796	0	0
RvalidKnown_A	222267032	222110796	0	0
WreadyKnown_A	222267032	222110796	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	222267032	531949	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222096736	483960	0	0
T4	147	0	0	0
T5	378	0	0	0
T9	4310	2086	0	0
T10	0	1601	0	0
T11	0	1191	0	0
T12	3004	704	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T19	0	475	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T31	0	2019	0	0
T43	1192	0	0	0
T48	0	444	0	0
T59	0	4430	0	0
T109	1102	0	0	0
T114	0	1480	0	0
T115	0	783	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	222110796	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	364	239	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	222110796	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	364	239	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	222110796	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	364	239	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	531949	0	0
T4	364	0	0	0
T5	1963	0	0	0
T9	4310	2086	0	0
T10	0	1601	0	0
T11	0	1191	0	0
T12	3004	704	0	0
T16	0	184	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T19	0	475	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T31	0	2019	0	0
T43	1192	0	0	0
T59	0	4430	0	0
T109	1102	0	0	0
T114	0	1480	0	0
T115	0	783	0	0