Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.97	96.97	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	96.97	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.97	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	1	20	95.24

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	1	20	95.24	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	144	1			T2	1		T26	1		T29	1
auto_req_mode	140	1			T9	1		T10	1		T38	1
sw_mode	3289	1			T1	1		T3	1		T6	8

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

281

1

T1

1

T2

1

T3

1

single

104

1

T9

1

T28

1

T35

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1440	1			T2	1		T3	1		T9	1
auto[2]	15	1			T242	4		T232	1		T243	1
auto[3]	217	1			T23	30		T24	71		T50	1
auto[4]	284	1			T152	1		T11	1		T25	57
auto[5]	149	1			T27	1		T32	1		T244	1
auto[6]	113	1			T26	1		T31	1		T178	1
auto[7]	1355	1			T1	1		T6	8		T10	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	1	20	95.24	1

Automatically Generated Cross Bins for cr_num_endpoints_mode

Uncovered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	NUMBER	STATUS
[auto[5]]	[auto_req_mode]	0	1	1

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	94	1			T2	1		T67	1		T95	1
auto[1]	auto_req_mode	82	1			T9	1		T38	1		T49	1
auto[1]	sw_mode	1264	1			T3	1		T143	1		T245	1
auto[2]	boot_req_mode	1	1			T246	1		-	-		-	-
auto[2]	auto_req_mode	4	1			T243	1		T247	1		T61	1
auto[2]	sw_mode	10	1			T242	4		T232	1		T198	4
auto[3]	boot_req_mode	4	1			T50	1		T248	1		T249	1
auto[3]	auto_req_mode	2	1			T250	1		T251	1		-	-
auto[3]	sw_mode	211	1			T23	30		T24	71		T252	9
auto[4]	boot_req_mode	2	1			T253	1		T254	1		-	-
auto[4]	auto_req_mode	3	1			T11	1		T255	1		T13	1
auto[4]	sw_mode	279	1			T152	1		T25	57		T256	78
auto[5]	boot_req_mode	3	1			T32	1		T257	1		T258	1
auto[5]	sw_mode	146	1			T27	1		T244	1		T259	1
auto[6]	boot_req_mode	8	1			T26	1		T260	1		T261	1
auto[6]	auto_req_mode	4	1			T262	1		T263	1		T264	1
auto[6]	sw_mode	101	1			T31	1		T178	1		T265	1
auto[7]	boot_req_mode	32	1			T29	1		T36	1		T34	1
auto[7]	auto_req_mode	45	1			T10	1		T30	1		T266	1
auto[7]	sw_mode	1278	1			T1	1		T6	8		T28	1