Group : tb.dut.u_edn_cov_if::edn_hw_cmd_sts_cg
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Group : tb.dut.u_edn_cov_if::edn_hw_cmd_sts_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_hw_cmd_sts_cg 100.00 1 100 1 64 64



Group Instance : edn_hw_cmd_sts_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance edn_hw_cmd_sts_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 12 0 12 100.00
Crosses 5 0 5 100.00


Variables for Group Instance edn_hw_cmd_sts_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_acmd 4 0 4 100.00 100 1 1 0
cp_auto_mode 2 0 2 100.00 100 1 1 0
cp_boot_mode 2 0 2 100.00 100 1 1 0
cp_cmd_ack 2 0 2 100.00 100 1 1 0
cp_cmd_sts 2 0 2 100.00 100 1 1 0


Crosses for Group Instance edn_hw_cmd_sts_cg
CROSS   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   PRINT MISSING   COMMENT   
cr_acmd_boot_mode 3 0 3 100.00 100 1 1 0
cr_acmd_auto_mode 2 0 2 100.00 100 1 1 0


Summary for Variable cp_acmd

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_acmd

Excluded/Illegal bins
NAME   COUNT   STATUS   
auto[INV] 0 Excluded
auto[UPD] 0 Excluded
auto[GENB] 0 Excluded
auto[GENU] 0 Excluded
unused 0 Excluded


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[INS] 18 1 T16 2 T17 1 T106 2
auto[RES] 8 1 T18 1 T170 1 T228 1
auto[GEN] 40 1 T17 1 T18 1 T70 1
auto[UNI] 10 1 T119 1 T170 1 T278 1


Summary for Variable cp_auto_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_auto_mode

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
not_auto_mode 75 1 T16 2 T17 2 T18 1
auto_mode 25 1 T18 1 T70 1 T71 1


Summary for Variable cp_boot_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_boot_mode

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
not_boot_mode 61 1 T17 1 T18 2 T70 2
boot_mode 39 1 T16 2 T17 1 T106 2


Summary for Variable cp_cmd_ack

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_cmd_ack

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
no_ack 49 1 T16 1 T17 1 T18 1
ack 51 1 T16 1 T17 1 T18 1


Summary for Variable cp_cmd_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_cmd_sts

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
success 49 1 T16 1 T17 1 T18 1
error 51 1 T16 1 T17 1 T18 1


Summary for Cross cr_acmd_boot_mode

Samples crossed: cp_acmd cp_boot_mode
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 3 0 3 100.00
Automatically Generated Cross Bins 3 0 3 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_acmd_boot_mode

Excluded/Illegal bins
cp_acmd   cp_boot_mode   COUNT   STATUS   
[auto[INV]] [not_boot_mode , boot_mode] -- Excluded (2 bins)
[auto[UPD]] [not_boot_mode , boot_mode] -- Excluded (2 bins)
[auto[GENB] , auto[GENU]] [not_boot_mode , boot_mode] -- Excluded (4 bins)


Covered bins
cp_acmd   cp_boot_mode   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[INS] boot_mode 18 1 T16 2 T17 1 T106 2
auto[GEN] boot_mode 11 1 T102 1 T103 1 T104 1
auto[UNI] boot_mode 8 1 T119 1 T120 1 T121 1


User Defined Cross Bins for cr_acmd_boot_mode

Excluded/Illegal bins
NAME   COUNT   STATUS   
not_boot_mode 0 Excluded
not_valid_boot_commands 0 Excluded


Summary for Cross cr_acmd_auto_mode

Samples crossed: cp_acmd cp_auto_mode
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for cr_acmd_auto_mode

Excluded/Illegal bins
cp_acmd   cp_auto_mode   COUNT   STATUS   
[auto[INV]] [not_auto_mode , auto_mode] -- Excluded (2 bins)
[auto[UPD]] [not_auto_mode , auto_mode] -- Excluded (2 bins)
[auto[GENB] , auto[GENU]] [not_auto_mode , auto_mode] -- Excluded (4 bins)


Covered bins
cp_acmd   cp_auto_mode   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[RES] auto_mode 8 1 T18 1 T170 1 T228 1
auto[GEN] auto_mode 17 1 T70 1 T71 1 T144 1


User Defined Cross Bins for cr_acmd_auto_mode

Excluded/Illegal bins
NAME   COUNT   STATUS   
not_auto_mode 0 Excluded
not_valid_boot_commands 0 Excluded