Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	695701	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5495576

1

T1

14

T2

34

T3

37

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1651525	1			T1	77		T2	110		T3	171
values[0x0]	2098992	1			T1	10		T2	19		T3	17
values[0x1]	2440760	1			T1	6		T2	13		T3	18

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	346721	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5844556

1

T1

39

T2

73

T3

82

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23901	1			T26	2		T23	104		T38	6
valid_sources[0x01]	22568	1			T3	1		T26	1		T23	103
valid_sources[0x02]	23016	1			T3	2		T23	105		T31	3
valid_sources[0x03]	23766	1			T1	1		T3	3		T26	1
valid_sources[0x04]	24200	1			T3	1		T10	1		T23	108
valid_sources[0x05]	24647	1			T1	2		T3	1		T23	97
valid_sources[0x06]	22225	1			T23	95		T153	1		T32	2
valid_sources[0x07]	22823	1			T3	1		T23	94		T30	4
valid_sources[0x08]	24261	1			T26	1		T23	127		T24	523
valid_sources[0x09]	24093	1			T23	90		T38	6		T67	1
valid_sources[0x0a]	23381	1			T23	107		T39	9		T288	1
valid_sources[0x0b]	24321	1			T26	1		T23	108		T39	4
valid_sources[0x0c]	23492	1			T1	2		T3	1		T26	1
valid_sources[0x0d]	23810	1			T23	108		T39	2		T24	553
valid_sources[0x0e]	22451	1			T23	106		T24	528		T33	1
valid_sources[0x0f]	23653	1			T1	1		T10	1		T23	100
valid_sources[0x10]	24060	1			T26	1		T23	136		T16	4
valid_sources[0x11]	23227	1			T26	1		T23	123		T153	1
valid_sources[0x12]	23697	1			T3	2		T26	1		T23	124
valid_sources[0x13]	25317	1			T1	2		T3	1		T26	3
valid_sources[0x14]	24269	1			T3	1		T23	108		T22	1
valid_sources[0x15]	22856	1			T10	2		T26	1		T23	114
valid_sources[0x16]	24586	1			T3	3		T23	102		T35	1
valid_sources[0x17]	25163	1			T3	1		T26	2		T23	90
valid_sources[0x18]	23873	1			T23	95		T153	2		T30	1
valid_sources[0x19]	23989	1			T23	109		T39	2		T11	1
valid_sources[0x1a]	22684	1			T1	1		T26	1		T23	124
valid_sources[0x1b]	23679	1			T3	1		T23	99		T11	2
valid_sources[0x1c]	24541	1			T3	1		T26	1		T23	107
valid_sources[0x1d]	24265	1			T3	1		T10	1		T23	108
valid_sources[0x1e]	24975	1			T23	101		T11	1		T7	1
valid_sources[0x1f]	23352	1			T1	1		T3	1		T23	92
valid_sources[0x20]	24904	1			T3	1		T23	121		T22	1
valid_sources[0x21]	23775	1			T3	1		T26	1		T23	107
valid_sources[0x22]	25036	1			T3	2		T10	1		T23	100
valid_sources[0x23]	24156	1			T1	3		T26	1		T23	103
valid_sources[0x24]	22825	1			T23	96		T39	2		T38	5
valid_sources[0x25]	24061	1			T1	1		T23	96		T31	5
valid_sources[0x26]	24753	1			T23	132		T35	2		T288	2
valid_sources[0x27]	24222	1			T3	1		T10	1		T23	118
valid_sources[0x28]	25853	1			T3	3		T26	2		T23	96
valid_sources[0x29]	24485	1			T23	108		T16	1		T39	2
valid_sources[0x2a]	23833	1			T1	1		T23	93		T39	1
valid_sources[0x2b]	24074	1			T3	1		T23	101		T39	2
valid_sources[0x2c]	24164	1			T1	1		T23	97		T16	1
valid_sources[0x2d]	24238	1			T3	1		T23	118		T39	2
valid_sources[0x2e]	23043	1			T26	1		T23	103		T39	1
valid_sources[0x2f]	24922	1			T3	1		T23	126		T7	1
valid_sources[0x30]	22704	1			T3	2		T23	117		T11	1
valid_sources[0x31]	24653	1			T23	101		T63	1		T152	6
valid_sources[0x32]	24849	1			T1	1		T3	2		T26	3
valid_sources[0x33]	25159	1			T3	1		T23	104		T22	1
valid_sources[0x34]	24498	1			T3	1		T23	116		T22	4
valid_sources[0x35]	24221	1			T3	1		T26	2		T23	96
valid_sources[0x36]	22999	1			T1	3		T26	1		T23	102
valid_sources[0x37]	23804	1			T2	142		T5	27		T23	119
valid_sources[0x38]	24084	1			T10	1		T23	110		T39	2
valid_sources[0x39]	23810	1			T3	1		T23	111		T39	1
valid_sources[0x3a]	23772	1			T1	2		T3	1		T26	1
valid_sources[0x3b]	26024	1			T3	1		T10	3		T23	109
valid_sources[0x3c]	26379	1			T3	1		T23	116		T24	497
valid_sources[0x3d]	22777	1			T3	3		T23	114		T153	3
valid_sources[0x3e]	24084	1			T10	1		T23	96		T22	4
valid_sources[0x3f]	23612	1			T1	1		T3	1		T23	102
valid_sources[0x40]	24126	1			T1	1		T3	2		T26	2
valid_sources[0x41]	23413	1			T26	1		T23	107		T31	1
valid_sources[0x42]	23774	1			T23	117		T63	1		T30	1
valid_sources[0x43]	21781	1			T26	1		T23	103		T16	1
valid_sources[0x44]	23419	1			T4	72		T26	2		T23	102
valid_sources[0x45]	25583	1			T26	1		T23	113		T31	4
valid_sources[0x46]	25627	1			T3	2		T10	1		T26	1
valid_sources[0x47]	22908	1			T23	137		T22	2		T152	4
valid_sources[0x48]	23939	1			T3	2		T10	2		T23	116
valid_sources[0x49]	23910	1			T3	2		T23	96		T11	1
valid_sources[0x4a]	24594	1			T23	105		T16	1		T31	1
valid_sources[0x4b]	24927	1			T3	1		T23	89		T11	1
valid_sources[0x4c]	23958	1			T10	2		T26	1		T23	108
valid_sources[0x4d]	24354	1			T3	3		T23	133		T32	2
valid_sources[0x4e]	23591	1			T1	2		T3	1		T23	101
valid_sources[0x4f]	23134	1			T10	2		T23	115		T31	2
valid_sources[0x50]	22991	1			T3	2		T26	1		T23	115
valid_sources[0x51]	24114	1			T3	2		T26	1		T23	91
valid_sources[0x52]	22050	1			T3	1		T26	1		T23	89
valid_sources[0x53]	25032	1			T26	1		T23	124		T153	1
valid_sources[0x54]	23616	1			T3	1		T26	2		T23	105
valid_sources[0x55]	22731	1			T3	1		T23	101		T153	2
valid_sources[0x56]	24876	1			T3	1		T26	2		T23	102
valid_sources[0x57]	24291	1			T1	1		T3	1		T26	1
valid_sources[0x58]	27105	1			T3	2		T23	97		T16	2
valid_sources[0x59]	25796	1			T3	1		T23	129		T22	2
valid_sources[0x5a]	24116	1			T1	1		T26	4		T23	117
valid_sources[0x5b]	23962	1			T23	104		T30	3		T24	520
valid_sources[0x5c]	24014	1			T1	1		T3	1		T26	1
valid_sources[0x5d]	24519	1			T3	2		T23	95		T22	4
valid_sources[0x5e]	24086	1			T3	1		T10	1		T26	1
valid_sources[0x5f]	24608	1			T3	1		T23	100		T30	2
valid_sources[0x60]	24938	1			T3	1		T23	107		T38	4
valid_sources[0x61]	23613	1			T3	1		T23	101		T153	1
valid_sources[0x62]	24987	1			T1	2		T23	105		T152	6
valid_sources[0x63]	23255	1			T10	2		T23	138		T24	472
valid_sources[0x64]	24457	1			T3	2		T23	124		T31	1
valid_sources[0x65]	25136	1			T10	1		T23	88		T153	1
valid_sources[0x66]	23766	1			T3	1		T26	1		T23	122
valid_sources[0x67]	23515	1			T1	1		T26	1		T23	104
valid_sources[0x68]	24700	1			T23	100		T39	2		T152	3
valid_sources[0x69]	25058	1			T3	1		T26	1		T23	89
valid_sources[0x6a]	25044	1			T23	110		T11	1		T32	1
valid_sources[0x6b]	24193	1			T26	2		T23	115		T35	51
valid_sources[0x6c]	25227	1			T3	1		T26	1		T23	113
valid_sources[0x6d]	24946	1			T3	2		T26	1		T23	97
valid_sources[0x6e]	24298	1			T10	3		T23	98		T16	1
valid_sources[0x6f]	24721	1			T3	1		T26	2		T23	109
valid_sources[0x70]	23836	1			T10	1		T23	118		T32	1
valid_sources[0x71]	25138	1			T26	1		T23	99		T22	2
valid_sources[0x72]	24016	1			T3	1		T26	1		T23	114
valid_sources[0x73]	23110	1			T3	1		T10	2		T23	96
valid_sources[0x74]	25576	1			T1	1		T26	1		T23	112
valid_sources[0x75]	24212	1			T1	1		T26	3		T23	116
valid_sources[0x76]	24077	1			T23	112		T28	142		T30	1
valid_sources[0x77]	23158	1			T1	2		T26	1		T23	123
valid_sources[0x78]	24375	1			T3	1		T23	105		T63	1
valid_sources[0x79]	25091	1			T3	1		T23	107		T24	531
valid_sources[0x7a]	23911	1			T3	1		T26	2		T23	108
valid_sources[0x7b]	24737	1			T3	1		T10	1		T23	90
valid_sources[0x7c]	24941	1			T3	1		T23	105		T63	1
valid_sources[0x7d]	24978	1			T3	2		T10	2		T26	1
valid_sources[0x7e]	22603	1			T3	1		T10	1		T23	105
valid_sources[0x7f]	24421	1			T3	2		T26	2		T23	106
valid_sources[0x80]	23331	1			T1	1		T26	2		T23	109

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1385493

1

T1

1

T2

6

T3

5

values[0x0]

all_enables

biggest_size

2055741

1

T1

8

T2

17

T3

14

values[0x1]

all_enables

biggest_size

2054342

1

T1

5

T2

11

T3

18