Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
67.19	67.19	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	67.19	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
67.19	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	21	31	59.62

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	21	31	59.62	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2808	1			T1	2		T3	1		T6	2
non_zero_bins[1]	1992	1			T2	2		T3	2		T6	1
zero	9468	1			T1	2		T2	6		T3	1

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	554	1			T3	1		T6	1		T23	2
uni	4034	1			T1	1		T2	3		T3	1
gen	4281	1			T1	1		T2	2		T3	1
res	869	1			T1	1		T9	3		T10	2
ins	4530	1			T1	1		T2	3		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9705

1

T1

3

T2

6

T3

2

mubi_true

4563

1

T1

1

T2

2

T3

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

50

1

T16

1

T17

1

T18

1

pass

14218

1

T1

4

T2

8

T3

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	21	31	59.62	21
Automatically Generated Cross Bins	52	21	31	59.62	21
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	4

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	135	1			T24	1		T25	4		T142	1
upd	non_zero_bins[0]	pass	mubi_true	128	1			T23	1		T28	1		T24	2
upd	non_zero_bins[1]	pass	mubi_false	84	1			T23	1		T35	1		T32	1
upd	non_zero_bins[1]	pass	mubi_true	87	1			T3	1		T24	1		T181	1
upd	zero	pass	mubi_false	58	1			T153	1		T24	1		T25	1
upd	zero	pass	mubi_true	62	1			T6	1		T24	1		T46	1
uni	zero	fail	mubi_false	8	1			T119	1		T120	1		T121	1
uni	zero	pass	mubi_false	2936	1			T1	1		T2	3		T3	1
uni	zero	pass	mubi_true	1090	1			T6	5		T23	12		T39	2
gen	non_zero_bins[0]	pass	mubi_false	532	1			T9	2		T23	4		T28	1
gen	non_zero_bins[0]	pass	mubi_true	512	1			T6	1		T10	2		T23	1
gen	non_zero_bins[1]	pass	mubi_false	358	1			T3	1		T23	1		T24	4
gen	non_zero_bins[1]	pass	mubi_true	362	1			T2	1		T23	3		T153	1
gen	zero	fail	mubi_false	26	1			T70	1		T71	1		T144	1
gen	zero	pass	mubi_false	2019	1			T1	1		T4	1		T5	1
gen	zero	pass	mubi_true	472	1			T2	1		T23	2		T16	2
res	non_zero_bins[0]	pass	mubi_false	196	1			T9	3		T10	2		T23	2
res	non_zero_bins[0]	pass	mubi_true	196	1			T1	1		T23	2		T24	1
res	non_zero_bins[1]	pass	mubi_false	124	1			T23	1		T39	1		T24	1
res	non_zero_bins[1]	pass	mubi_true	140	1			T23	1		T152	1		T24	4
res	zero	fail	mubi_false	8	1			T18	1		T170	1		T228	1
res	zero	pass	mubi_false	103	1			T11	2		T24	2		T229	3
res	zero	pass	mubi_true	102	1			T38	4		T30	2		T24	1
ins	non_zero_bins[0]	pass	mubi_false	571	1			T1	1		T26	1		T23	4
ins	non_zero_bins[0]	pass	mubi_true	538	1			T3	1		T6	1		T23	5
ins	non_zero_bins[1]	pass	mubi_false	405	1			T2	1		T6	1		T23	2
ins	non_zero_bins[1]	pass	mubi_true	432	1			T23	1		T38	1		T153	1
ins	zero	fail	mubi_false	5	1			T16	1		T106	1		T147	1
ins	zero	fail	mubi_true	3	1			T17	1		T230	1		T231	1
ins	zero	pass	mubi_false	2137	1			T2	2		T4	1		T5	1
ins	zero	pass	mubi_true	439	1			T6	1		T9	1		T10	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded