Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	215978954	9722129	0	0
boot_gen_cmd_rd_A	215978954	54427	0	0
boot_ins_cmd_rd_A	215978954	61527	0	0
ctrl_rd_A	215978954	54849	0	0
err_code_test_rd_A	215978954	63124	0	0
intr_enable_rd_A	215978954	59844	0	0
max_num_reqs_between_reseeds_rd_A	215978954	55679	0	0
regwen_rd_A	215978954	64556	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215978954	9722129	0	0
T16	2323	0	0	0
T22	1298	0	0	0
T23	125123	41803	0	0
T24	0	210683	0	0
T25	0	286493	0	0
T28	2383	0	0	0
T29	2921	0	0	0
T35	1824	0	0	0
T38	2810	0	0	0
T39	11161	0	0	0
T63	1205	0	0	0
T142	0	114751	0	0
T152	4845	0	0	0
T181	0	261736	0	0
T182	0	211315	0	0
T183	0	51539	0	0
T184	0	299303	0	0
T185	0	285594	0	0
T186	0	159930	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215978954	54427	0	0
T16	2323	0	0	0
T22	1298	0	0	0
T23	125123	1188	0	0
T24	0	6202	0	0
T28	2383	0	0	0
T29	2921	0	0	0
T35	1824	0	0	0
T38	2810	0	0	0
T39	11161	0	0	0
T63	1205	0	0	0
T142	0	3220	0	0
T152	4845	0	0	0
T181	0	7755	0	0
T187	0	1593	0	0
T188	0	3757	0	0
T189	0	537	0	0
T190	0	1420	0	0
T191	0	8198	0	0
T192	0	2326	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215978954	61527	0	0
T16	2323	0	0	0
T22	1298	0	0	0
T23	125123	1393	0	0
T24	0	7412	0	0
T28	2383	0	0	0
T29	2921	0	0	0
T35	1824	0	0	0
T38	2810	0	0	0
T39	11161	0	0	0
T63	1205	0	0	0
T142	0	3684	0	0
T152	4845	0	0	0
T181	0	8743	0	0
T187	0	1657	0	0
T188	0	4109	0	0
T189	0	580	0	0
T190	0	1559	0	0
T191	0	9236	0	0
T192	0	2608	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215978954	54849	0	0
T16	2323	0	0	0
T22	1298	0	0	0
T23	125123	1336	0	0
T24	0	6253	0	0
T28	2383	0	0	0
T29	2921	0	0	0
T35	1824	0	0	0
T38	2810	0	0	0
T39	11161	4	0	0
T63	1205	0	0	0
T142	0	3162	0	0
T152	4845	0	0	0
T181	0	7350	0	0
T187	0	1442	0	0
T188	0	3902	0	0
T193	0	5	0	0
T194	0	1	0	0
T195	0	3	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215978954	63124	0	0
T16	2323	0	0	0
T22	1298	0	0	0
T23	125123	1454	0	0
T24	0	7098	0	0
T28	2383	0	0	0
T29	2921	0	0	0
T35	1824	0	0	0
T38	2810	0	0	0
T39	11161	0	0	0
T63	1205	0	0	0
T142	0	3748	0	0
T152	4845	0	0	0
T181	0	8886	0	0
T187	0	1670	0	0
T188	0	4378	0	0
T189	0	594	0	0
T190	0	1717	0	0
T191	0	9791	0	0
T192	0	2516	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215978954	59844	0	0
T16	2323	0	0	0
T22	1298	0	0	0
T23	125123	1510	0	0
T24	0	7039	0	0
T28	2383	0	0	0
T29	2921	0	0	0
T35	1824	0	0	0
T38	2810	0	0	0
T39	11161	27	0	0
T63	1205	0	0	0
T142	0	3867	0	0
T152	4845	0	0	0
T181	0	7575	0	0
T187	0	1805	0	0
T188	0	3820	0	0
T196	0	168	0	0
T197	0	47	0	0
T198	0	25	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215978954	55679	0	0
T16	2323	0	0	0
T22	1298	0	0	0
T23	125123	1261	0	0
T24	0	6211	0	0
T28	2383	0	0	0
T29	2921	0	0	0
T35	1824	0	0	0
T38	2810	0	0	0
T39	11161	0	0	0
T63	1205	0	0	0
T142	0	3149	0	0
T152	4845	0	0	0
T181	0	7815	0	0
T187	0	1524	0	0
T188	0	3741	0	0
T189	0	469	0	0
T190	0	1396	0	0
T191	0	8550	0	0
T192	0	2194	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215978954	64556	0	0
T16	2323	0	0	0
T22	1298	0	0	0
T23	125123	1339	0	0
T24	0	7504	0	0
T28	2383	0	0	0
T29	2921	0	0	0
T35	1824	0	0	0
T38	2810	0	0	0
T39	11161	0	0	0
T63	1205	0	0	0
T142	0	3789	0	0
T152	4845	0	0	0
T181	0	9023	0	0
T187	0	1644	0	0
T188	0	4470	0	0
T189	0	543	0	0
T190	0	1587	0	0
T191	0	9457	0	0
T192	0	2542	0	0