Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	93.75	100.00	75.00			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	95.31	100.00	81.25			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.89			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T123,T124,T125
1	0	1	Covered	T4,T5,T9
1	1	0	Not Covered
1	1	1	Covered	T4,T9,T10

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T9
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T9

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	430536878	1000725	0	0
DepthKnown_A	430901496	430613242	0	0
RvalidKnown_A	430901496	430613242	0	0
WreadyKnown_A	430901496	430613242	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	430901496	1091480	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430536878	1000725	0	0
T4	238	67	0	0
T5	938	0	0	0
T6	20578	0	0	0
T7	0	145	0	0
T9	2952	1719	0	0
T10	9696	6976	0	0
T11	0	1970	0	0
T18	0	625	0	0
T22	698	0	0	0
T23	250246	0	0	0
T26	4768	0	0	0
T27	4398	0	0	0
T30	0	1486	0	0
T38	0	2980	0	0
T49	0	1379	0	0
T63	236	0	0	0
T126	0	5108	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430901496	430613242	0	0
T1	4898	4736	0	0
T2	5368	5186	0	0
T3	9032	8872	0	0
T4	3934	3680	0	0
T5	4280	3940	0	0
T6	20578	19930	0	0
T9	2952	2848	0	0
T10	9696	9542	0	0
T26	4768	4632	0	0
T27	4398	4290	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430901496	430613242	0	0
T1	4898	4736	0	0
T2	5368	5186	0	0
T3	9032	8872	0	0
T4	3934	3680	0	0
T5	4280	3940	0	0
T6	20578	19930	0	0
T9	2952	2848	0	0
T10	9696	9542	0	0
T26	4768	4632	0	0
T27	4398	4290	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	430901496	430613242	0	0
T1	4898	4736	0	0
T2	5368	5186	0	0
T3	9032	8872	0	0
T4	3934	3680	0	0
T5	4280	3940	0	0
T6	20578	19930	0	0
T9	2952	2848	0	0
T10	9696	9542	0	0
T26	4768	4632	0	0
T27	4398	4290	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	430901496	1091480	0	0
T4	3934	1611	0	0
T5	4280	21	0	0
T6	20578	0	0	0
T7	0	769	0	0
T9	2952	1719	0	0
T10	9696	6976	0	0
T11	0	1970	0	0
T22	2596	0	0	0
T23	250246	0	0	0
T26	4768	0	0	0
T27	4398	0	0	0
T30	0	1486	0	0
T38	0	2980	0	0
T63	2410	319	0	0
T64	0	439	0	0
T66	0	115	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T9,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T4,T9,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T124,T125,T127
1	0	1	Covered	T4,T9,T10
1	1	0	Not Covered
1	1	1	Covered	T4,T9,T10

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T9,T10
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T9,T10

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	215268439	505564	0	0
DepthKnown_A	215450748	215306621	0	0
RvalidKnown_A	215450748	215306621	0	0
WreadyKnown_A	215450748	215306621	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	215450748	551394	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215268439	505564	0	0
T4	119	44	0	0
T5	469	0	0	0
T6	10289	0	0	0
T7	0	116	0	0
T9	1476	925	0	0
T10	4848	3541	0	0
T11	0	999	0	0
T18	0	311	0	0
T22	349	0	0	0
T23	125123	0	0	0
T26	2384	0	0	0
T27	2199	0	0	0
T30	0	793	0	0
T38	0	1554	0	0
T49	0	704	0	0
T63	118	0	0	0
T126	0	2585	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215450748	215306621	0	0
T1	2449	2368	0	0
T2	2684	2593	0	0
T3	4516	4436	0	0
T4	1967	1840	0	0
T5	2140	1970	0	0
T6	10289	9965	0	0
T9	1476	1424	0	0
T10	4848	4771	0	0
T26	2384	2316	0	0
T27	2199	2145	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215450748	215306621	0	0
T1	2449	2368	0	0
T2	2684	2593	0	0
T3	4516	4436	0	0
T4	1967	1840	0	0
T5	2140	1970	0	0
T6	10289	9965	0	0
T9	1476	1424	0	0
T10	4848	4771	0	0
T26	2384	2316	0	0
T27	2199	2145	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215450748	215306621	0	0
T1	2449	2368	0	0
T2	2684	2593	0	0
T3	4516	4436	0	0
T4	1967	1840	0	0
T5	2140	1970	0	0
T6	10289	9965	0	0
T9	1476	1424	0	0
T10	4848	4771	0	0
T26	2384	2316	0	0
T27	2199	2145	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	215450748	551394	0	0
T4	1967	825	0	0
T5	2140	0	0	0
T6	10289	0	0	0
T7	0	459	0	0
T9	1476	925	0	0
T10	4848	3541	0	0
T11	0	999	0	0
T22	1298	0	0	0
T23	125123	0	0	0
T26	2384	0	0	0
T27	2199	0	0	0
T30	0	793	0	0
T38	0	1554	0	0
T63	1205	157	0	0
T64	0	213	0	0
T66	0	115	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T128,T45
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T5,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T5
1	1	0	Not Covered
1	1	1	Covered	T4,T5,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T123,T129,T130
1	0	1	Covered	T4,T5,T9
1	1	0	Not Covered
1	1	1	Covered	T9,T10,T38

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T5,T9
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T9

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	215268439	495161	0	0
DepthKnown_A	215450748	215306621	0	0
RvalidKnown_A	215450748	215306621	0	0
WreadyKnown_A	215450748	215306621	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	215450748	540086	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215268439	495161	0	0
T4	119	23	0	0
T5	469	0	0	0
T6	10289	0	0	0
T7	0	29	0	0
T9	1476	794	0	0
T10	4848	3435	0	0
T11	0	971	0	0
T18	0	314	0	0
T22	349	0	0	0
T23	125123	0	0	0
T26	2384	0	0	0
T27	2199	0	0	0
T30	0	693	0	0
T38	0	1426	0	0
T49	0	675	0	0
T63	118	0	0	0
T126	0	2523	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215450748	215306621	0	0
T1	2449	2368	0	0
T2	2684	2593	0	0
T3	4516	4436	0	0
T4	1967	1840	0	0
T5	2140	1970	0	0
T6	10289	9965	0	0
T9	1476	1424	0	0
T10	4848	4771	0	0
T26	2384	2316	0	0
T27	2199	2145	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215450748	215306621	0	0
T1	2449	2368	0	0
T2	2684	2593	0	0
T3	4516	4436	0	0
T4	1967	1840	0	0
T5	2140	1970	0	0
T6	10289	9965	0	0
T9	1476	1424	0	0
T10	4848	4771	0	0
T26	2384	2316	0	0
T27	2199	2145	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215450748	215306621	0	0
T1	2449	2368	0	0
T2	2684	2593	0	0
T3	4516	4436	0	0
T4	1967	1840	0	0
T5	2140	1970	0	0
T6	10289	9965	0	0
T9	1476	1424	0	0
T10	4848	4771	0	0
T26	2384	2316	0	0
T27	2199	2145	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	215450748	540086	0	0
T4	1967	786	0	0
T5	2140	21	0	0
T6	10289	0	0	0
T7	0	310	0	0
T9	1476	794	0	0
T10	4848	3435	0	0
T11	0	971	0	0
T22	1298	0	0	0
T23	125123	0	0	0
T26	2384	0	0	0
T27	2199	0	0	0
T30	0	693	0	0
T38	0	1426	0	0
T63	1205	162	0	0
T64	0	226	0	0