Line Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 23 | 23 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
Line Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 162 |
1 |
1 |
Cond Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=128,ClearOnRead=0,MaxW=128,MinW=128,DepthW=0 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T5 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T9,T38,T49 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_packer_fifo ( parameter InW=128,OutW=32,ClearOnRead=0,MaxW=128,MinW=32,DepthW=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T18,T102,T103 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_packer_fifo
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
141 |
4 |
4 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_packer_fifo
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1723605984 |
197694749 |
0 |
6400 |
| T1 |
7347 |
5058 |
0 |
3 |
| T2 |
13420 |
1816 |
0 |
5 |
| T3 |
22580 |
2465 |
0 |
5 |
| T4 |
11802 |
0 |
0 |
6 |
| T5 |
12840 |
1041 |
0 |
6 |
| T6 |
61734 |
8357 |
0 |
6 |
| T9 |
8856 |
0 |
0 |
6 |
| T10 |
38784 |
19208 |
0 |
8 |
| T11 |
0 |
4978 |
0 |
0 |
| T16 |
4646 |
1333 |
0 |
2 |
| T22 |
3894 |
505 |
0 |
3 |
| T23 |
625615 |
123038 |
0 |
5 |
| T26 |
19072 |
8537 |
0 |
8 |
| T27 |
17592 |
4244 |
0 |
8 |
| T28 |
4766 |
4603 |
0 |
2 |
| T29 |
0 |
7926 |
0 |
0 |
| T30 |
0 |
4051 |
0 |
0 |
| T31 |
0 |
3887 |
0 |
0 |
| T32 |
0 |
4359 |
0 |
0 |
| T33 |
0 |
3780 |
0 |
0 |
| T35 |
3648 |
0 |
0 |
2 |
| T39 |
22322 |
5099 |
0 |
2 |
| T63 |
3615 |
0 |
0 |
3 |
| T67 |
0 |
1019 |
0 |
0 |
| T152 |
0 |
11790 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1723605984 |
197694749 |
0 |
0 |
| T1 |
7347 |
5058 |
0 |
0 |
| T2 |
13420 |
1816 |
0 |
0 |
| T3 |
22580 |
2465 |
0 |
0 |
| T4 |
11802 |
0 |
0 |
0 |
| T5 |
12840 |
1041 |
0 |
0 |
| T6 |
61734 |
8357 |
0 |
0 |
| T9 |
8856 |
0 |
0 |
0 |
| T10 |
38784 |
19208 |
0 |
0 |
| T11 |
0 |
4978 |
0 |
0 |
| T16 |
4646 |
1333 |
0 |
0 |
| T22 |
3894 |
505 |
0 |
0 |
| T23 |
625615 |
123038 |
0 |
0 |
| T26 |
19072 |
8537 |
0 |
0 |
| T27 |
17592 |
4244 |
0 |
0 |
| T28 |
4766 |
4603 |
0 |
0 |
| T29 |
0 |
7926 |
0 |
0 |
| T30 |
0 |
4051 |
0 |
0 |
| T31 |
0 |
3887 |
0 |
0 |
| T32 |
0 |
4359 |
0 |
0 |
| T33 |
0 |
3780 |
0 |
0 |
| T35 |
3648 |
0 |
0 |
0 |
| T39 |
22322 |
5099 |
0 |
0 |
| T63 |
3615 |
0 |
0 |
0 |
| T67 |
0 |
1019 |
0 |
0 |
| T152 |
0 |
11790 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 23 | 23 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T5 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T5 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T9,T38,T49 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
12 |
85.71 |
| TERNARY |
141 |
4 |
3 |
75.00 |
| TERNARY |
146 |
3 |
2 |
66.67 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Not Covered |
|
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Not Covered |
|
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_packer_fifo_cs
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215450748 |
111501 |
0 |
800 |
| T2 |
2684 |
6 |
0 |
1 |
| T3 |
4516 |
4 |
0 |
1 |
| T4 |
1967 |
0 |
0 |
1 |
| T5 |
2140 |
29 |
0 |
1 |
| T6 |
10289 |
0 |
0 |
1 |
| T9 |
1476 |
407 |
0 |
1 |
| T10 |
4848 |
641 |
0 |
1 |
| T16 |
0 |
116 |
0 |
0 |
| T22 |
0 |
42 |
0 |
0 |
| T23 |
125123 |
0 |
0 |
1 |
| T26 |
2384 |
23 |
0 |
1 |
| T27 |
2199 |
19 |
0 |
1 |
| T35 |
0 |
48 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215450748 |
111501 |
0 |
0 |
| T2 |
2684 |
6 |
0 |
0 |
| T3 |
4516 |
4 |
0 |
0 |
| T4 |
1967 |
0 |
0 |
0 |
| T5 |
2140 |
29 |
0 |
0 |
| T6 |
10289 |
0 |
0 |
0 |
| T9 |
1476 |
407 |
0 |
0 |
| T10 |
4848 |
641 |
0 |
0 |
| T16 |
0 |
116 |
0 |
0 |
| T22 |
0 |
42 |
0 |
0 |
| T23 |
125123 |
0 |
0 |
0 |
| T26 |
2384 |
23 |
0 |
0 |
| T27 |
2199 |
19 |
0 |
0 |
| T35 |
0 |
48 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T2,T3,T6 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T6 |
| 1 | 0 | Covered | T2,T3,T6 |
| 1 | 1 | Covered | T2,T3,T6 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T6 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T2,T3,T6 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T2,T3,T6 |
| 1 | 1 | Covered | T2,T3,T6 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T6 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T6 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T6 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T3,T6 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T6 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T18,T170,T104 |
| 1 | 1 | Covered | T2,T3,T6 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T2,T3,T6 |
| 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
141 |
4 |
4 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T2,T3,T6 |
| 0 |
0 |
1 |
Covered |
T2,T3,T6 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T3,T6 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T2,T3,T6 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215450748 |
196315660 |
0 |
800 |
| T2 |
2684 |
1816 |
0 |
1 |
| T3 |
4516 |
2465 |
0 |
1 |
| T4 |
1967 |
0 |
0 |
1 |
| T5 |
2140 |
0 |
0 |
1 |
| T6 |
10289 |
8357 |
0 |
1 |
| T9 |
1476 |
0 |
0 |
1 |
| T10 |
4848 |
4207 |
0 |
1 |
| T16 |
0 |
1333 |
0 |
0 |
| T23 |
125123 |
123038 |
0 |
1 |
| T26 |
2384 |
1303 |
0 |
1 |
| T27 |
2199 |
0 |
0 |
1 |
| T28 |
0 |
1444 |
0 |
0 |
| T39 |
0 |
5099 |
0 |
0 |
| T152 |
0 |
2993 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215450748 |
196315660 |
0 |
0 |
| T2 |
2684 |
1816 |
0 |
0 |
| T3 |
4516 |
2465 |
0 |
0 |
| T4 |
1967 |
0 |
0 |
0 |
| T5 |
2140 |
0 |
0 |
0 |
| T6 |
10289 |
8357 |
0 |
0 |
| T9 |
1476 |
0 |
0 |
0 |
| T10 |
4848 |
4207 |
0 |
0 |
| T16 |
0 |
1333 |
0 |
0 |
| T23 |
125123 |
123038 |
0 |
0 |
| T26 |
2384 |
1303 |
0 |
0 |
| T27 |
2199 |
0 |
0 |
0 |
| T28 |
0 |
1444 |
0 |
0 |
| T39 |
0 |
5099 |
0 |
0 |
| T152 |
0 |
2993 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T10,T26 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T10,T26 |
| 1 | 0 | Covered | T1,T5,T10 |
| 1 | 1 | Covered | T1,T10,T26 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T10,T26 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T5,T10 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T5,T10 |
| 1 | 1 | Covered | T1,T5,T10 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T5,T10 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T5,T10 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T5,T10 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T5,T10 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T5,T10 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T102,T120,T171 |
| 1 | 1 | Covered | T1,T5,T10 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T5,T10 |
| 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
141 |
4 |
4 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T5,T10 |
| 0 |
0 |
1 |
Covered |
T1,T5,T10 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T5,T10 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T5,T10 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215450748 |
210738 |
0 |
800 |
| T1 |
2449 |
1700 |
0 |
1 |
| T2 |
2684 |
0 |
0 |
1 |
| T3 |
4516 |
0 |
0 |
1 |
| T4 |
1967 |
0 |
0 |
1 |
| T5 |
2140 |
1041 |
0 |
1 |
| T6 |
10289 |
0 |
0 |
1 |
| T9 |
1476 |
0 |
0 |
1 |
| T10 |
4848 |
4294 |
0 |
1 |
| T11 |
0 |
1950 |
0 |
0 |
| T26 |
2384 |
2233 |
0 |
1 |
| T27 |
2199 |
1653 |
0 |
1 |
| T29 |
0 |
2193 |
0 |
0 |
| T30 |
0 |
943 |
0 |
0 |
| T31 |
0 |
1235 |
0 |
0 |
| T152 |
0 |
2964 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215450748 |
210738 |
0 |
0 |
| T1 |
2449 |
1700 |
0 |
0 |
| T2 |
2684 |
0 |
0 |
0 |
| T3 |
4516 |
0 |
0 |
0 |
| T4 |
1967 |
0 |
0 |
0 |
| T5 |
2140 |
1041 |
0 |
0 |
| T6 |
10289 |
0 |
0 |
0 |
| T9 |
1476 |
0 |
0 |
0 |
| T10 |
4848 |
4294 |
0 |
0 |
| T11 |
0 |
1950 |
0 |
0 |
| T26 |
2384 |
2233 |
0 |
0 |
| T27 |
2199 |
1653 |
0 |
0 |
| T29 |
0 |
2193 |
0 |
0 |
| T30 |
0 |
943 |
0 |
0 |
| T31 |
0 |
1235 |
0 |
0 |
| T152 |
0 |
2964 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T10,T26 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T10,T26 |
| 1 | 0 | Covered | T1,T10,T26 |
| 1 | 1 | Covered | T1,T10,T26 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T10,T26 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T10,T26 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T10,T26 |
| 1 | 1 | Covered | T1,T10,T26 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T10,T26 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T10,T26 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T10,T26 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T10,T26 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T10,T26 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T103,T100,T172 |
| 1 | 1 | Covered | T1,T10,T26 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T10,T26 |
| 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
141 |
4 |
4 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T10,T26 |
| 0 |
0 |
1 |
Covered |
T1,T10,T26 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T10,T26 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T10,T26 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215450748 |
219597 |
0 |
800 |
| T1 |
2449 |
1687 |
0 |
1 |
| T2 |
2684 |
0 |
0 |
1 |
| T3 |
4516 |
0 |
0 |
1 |
| T4 |
1967 |
0 |
0 |
1 |
| T5 |
2140 |
0 |
0 |
1 |
| T6 |
10289 |
0 |
0 |
1 |
| T9 |
1476 |
0 |
0 |
1 |
| T10 |
4848 |
4196 |
0 |
1 |
| T11 |
0 |
1901 |
0 |
0 |
| T26 |
2384 |
2224 |
0 |
1 |
| T27 |
2199 |
1282 |
0 |
1 |
| T28 |
0 |
1418 |
0 |
0 |
| T29 |
0 |
1759 |
0 |
0 |
| T30 |
0 |
1075 |
0 |
0 |
| T31 |
0 |
1375 |
0 |
0 |
| T152 |
0 |
2930 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215450748 |
219597 |
0 |
0 |
| T1 |
2449 |
1687 |
0 |
0 |
| T2 |
2684 |
0 |
0 |
0 |
| T3 |
4516 |
0 |
0 |
0 |
| T4 |
1967 |
0 |
0 |
0 |
| T5 |
2140 |
0 |
0 |
0 |
| T6 |
10289 |
0 |
0 |
0 |
| T9 |
1476 |
0 |
0 |
0 |
| T10 |
4848 |
4196 |
0 |
0 |
| T11 |
0 |
1901 |
0 |
0 |
| T26 |
2384 |
2224 |
0 |
0 |
| T27 |
2199 |
1282 |
0 |
0 |
| T28 |
0 |
1418 |
0 |
0 |
| T29 |
0 |
1759 |
0 |
0 |
| T30 |
0 |
1075 |
0 |
0 |
| T31 |
0 |
1375 |
0 |
0 |
| T152 |
0 |
2930 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T10,T26,T27 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T10,T26,T27 |
| 1 | 0 | Covered | T10,T26,T27 |
| 1 | 1 | Covered | T10,T26,T27 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T10,T26,T27 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T10,T26,T27 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T10,T26,T27 |
| 1 | 1 | Covered | T10,T26,T27 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T10,T26,T27 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T10,T26,T27 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T10,T26,T27 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T10,T26,T27 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T10,T26,T27 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T97,T119,T169 |
| 1 | 1 | Covered | T10,T26,T27 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T10,T26,T27 |
| 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
141 |
4 |
4 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T10,T26,T27 |
| 0 |
0 |
1 |
Covered |
T10,T26,T27 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T10,T26,T27 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T10,T26,T27 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215450748 |
199933 |
0 |
800 |
| T10 |
4848 |
4253 |
0 |
1 |
| T11 |
0 |
1127 |
0 |
0 |
| T16 |
2323 |
0 |
0 |
1 |
| T22 |
1298 |
0 |
0 |
1 |
| T23 |
125123 |
0 |
0 |
1 |
| T26 |
2384 |
1332 |
0 |
1 |
| T27 |
2199 |
1309 |
0 |
1 |
| T28 |
2383 |
1741 |
0 |
1 |
| T29 |
0 |
1776 |
0 |
0 |
| T30 |
0 |
2033 |
0 |
0 |
| T32 |
0 |
2125 |
0 |
0 |
| T33 |
0 |
1712 |
0 |
0 |
| T35 |
1824 |
0 |
0 |
1 |
| T39 |
11161 |
0 |
0 |
1 |
| T63 |
1205 |
0 |
0 |
1 |
| T152 |
0 |
2903 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215450748 |
199933 |
0 |
0 |
| T10 |
4848 |
4253 |
0 |
0 |
| T11 |
0 |
1127 |
0 |
0 |
| T16 |
2323 |
0 |
0 |
0 |
| T22 |
1298 |
0 |
0 |
0 |
| T23 |
125123 |
0 |
0 |
0 |
| T26 |
2384 |
1332 |
0 |
0 |
| T27 |
2199 |
1309 |
0 |
0 |
| T28 |
2383 |
1741 |
0 |
0 |
| T29 |
0 |
1776 |
0 |
0 |
| T30 |
0 |
2033 |
0 |
0 |
| T32 |
0 |
2125 |
0 |
0 |
| T33 |
0 |
1712 |
0 |
0 |
| T35 |
1824 |
0 |
0 |
0 |
| T39 |
11161 |
0 |
0 |
0 |
| T63 |
1205 |
0 |
0 |
0 |
| T152 |
0 |
2903 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T10,T26 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T10,T26 |
| 1 | 0 | Covered | T1,T10,T26 |
| 1 | 1 | Covered | T1,T10,T26 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T10,T26 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T10,T26 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T1,T10,T26 |
| 1 | 1 | Covered | T1,T10,T26 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T10,T26 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T10,T26 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T10,T26 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T10,T26 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T10,T26 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T96,T116,T173 |
| 1 | 1 | Covered | T1,T10,T26 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T10,T26 |
| 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
141 |
4 |
4 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T10,T26 |
| 0 |
0 |
1 |
Covered |
T1,T10,T26 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T10,T26 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T10,T26 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215450748 |
193078 |
0 |
800 |
| T1 |
2449 |
1671 |
0 |
1 |
| T2 |
2684 |
0 |
0 |
1 |
| T3 |
4516 |
0 |
0 |
1 |
| T4 |
1967 |
0 |
0 |
1 |
| T5 |
2140 |
0 |
0 |
1 |
| T6 |
10289 |
0 |
0 |
1 |
| T9 |
1476 |
0 |
0 |
1 |
| T10 |
4848 |
2258 |
0 |
1 |
| T22 |
0 |
505 |
0 |
0 |
| T26 |
2384 |
1445 |
0 |
1 |
| T27 |
2199 |
0 |
0 |
1 |
| T29 |
0 |
2198 |
0 |
0 |
| T31 |
0 |
1277 |
0 |
0 |
| T32 |
0 |
2234 |
0 |
0 |
| T33 |
0 |
2068 |
0 |
0 |
| T67 |
0 |
1019 |
0 |
0 |
| T174 |
0 |
1896 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215450748 |
193078 |
0 |
0 |
| T1 |
2449 |
1671 |
0 |
0 |
| T2 |
2684 |
0 |
0 |
0 |
| T3 |
4516 |
0 |
0 |
0 |
| T4 |
1967 |
0 |
0 |
0 |
| T5 |
2140 |
0 |
0 |
0 |
| T6 |
10289 |
0 |
0 |
0 |
| T9 |
1476 |
0 |
0 |
0 |
| T10 |
4848 |
2258 |
0 |
0 |
| T22 |
0 |
505 |
0 |
0 |
| T26 |
2384 |
1445 |
0 |
0 |
| T27 |
2199 |
0 |
0 |
0 |
| T29 |
0 |
2198 |
0 |
0 |
| T31 |
0 |
1277 |
0 |
0 |
| T32 |
0 |
2234 |
0 |
0 |
| T33 |
0 |
2068 |
0 |
0 |
| T67 |
0 |
1019 |
0 |
0 |
| T174 |
0 |
1896 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T10,T28,T29 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T10,T28,T29 |
| 1 | 0 | Covered | T10,T28,T29 |
| 1 | 1 | Covered | T10,T28,T29 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T10,T28,T29 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T10,T28,T29 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T10,T28,T29 |
| 1 | 1 | Covered | T10,T28,T29 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T10,T28,T29 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T10,T28,T29 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T10,T28,T29 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T10,T28,T29 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T10,T28,T29 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T175,T176,T177 |
| 1 | 1 | Covered | T10,T28,T29 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T10,T28,T29 |
| 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
141 |
4 |
4 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T10,T28,T29 |
| 0 |
0 |
1 |
Covered |
T10,T28,T29 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T10,T28,T29 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T10,T28,T29 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215450748 |
198429 |
0 |
800 |
| T10 |
4848 |
4072 |
0 |
1 |
| T16 |
2323 |
0 |
0 |
1 |
| T22 |
1298 |
0 |
0 |
1 |
| T23 |
125123 |
0 |
0 |
1 |
| T26 |
2384 |
0 |
0 |
1 |
| T27 |
2199 |
0 |
0 |
1 |
| T28 |
2383 |
1532 |
0 |
1 |
| T29 |
0 |
2196 |
0 |
0 |
| T30 |
0 |
2016 |
0 |
0 |
| T33 |
0 |
1686 |
0 |
0 |
| T34 |
0 |
1192 |
0 |
0 |
| T35 |
1824 |
0 |
0 |
1 |
| T36 |
0 |
2920 |
0 |
0 |
| T39 |
11161 |
0 |
0 |
1 |
| T63 |
1205 |
0 |
0 |
1 |
| T174 |
0 |
1865 |
0 |
0 |
| T178 |
0 |
1489 |
0 |
0 |
| T179 |
0 |
2621 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215450748 |
198429 |
0 |
0 |
| T10 |
4848 |
4072 |
0 |
0 |
| T16 |
2323 |
0 |
0 |
0 |
| T22 |
1298 |
0 |
0 |
0 |
| T23 |
125123 |
0 |
0 |
0 |
| T26 |
2384 |
0 |
0 |
0 |
| T27 |
2199 |
0 |
0 |
0 |
| T28 |
2383 |
1532 |
0 |
0 |
| T29 |
0 |
2196 |
0 |
0 |
| T30 |
0 |
2016 |
0 |
0 |
| T33 |
0 |
1686 |
0 |
0 |
| T34 |
0 |
1192 |
0 |
0 |
| T35 |
1824 |
0 |
0 |
0 |
| T36 |
0 |
2920 |
0 |
0 |
| T39 |
11161 |
0 |
0 |
0 |
| T63 |
1205 |
0 |
0 |
0 |
| T174 |
0 |
1865 |
0 |
0 |
| T178 |
0 |
1489 |
0 |
0 |
| T179 |
0 |
2621 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 24 | 24 | 100.00 |
| ALWAYS | 81 | 7 | 7 | 100.00 |
| CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
| ALWAYS | 126 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 135 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 136 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 137 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements | |
| 81 |
1 |
1 |
| 82 |
1 |
1 |
| 83 |
1 |
1 |
| 84 |
1 |
1 |
| 86 |
1 |
1 |
| 87 |
1 |
1 |
| 88 |
1 |
1 |
| 93 |
1 |
1 |
| 95 |
1 |
1 |
| 126 |
1 |
1 |
| 127 |
1 |
1 |
| 129 |
1 |
1 |
| 135 |
1 |
1 |
| 136 |
1 |
1 |
| 137 |
1 |
1 |
| 138 |
1 |
1 |
| 139 |
1 |
1 |
| 141 |
1 |
1 |
| 146 |
1 |
1 |
| 150 |
1 |
1 |
| 155 |
1 |
1 |
| 156 |
1 |
1 |
| 157 |
1 |
1 |
| 162 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
| Total | Covered | Percent |
|---|
| Conditions | 42 | 40 | 95.24 |
| Logical | 42 | 40 | 95.24 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 136
EXPRESSION ((rready_i && (depth_q == gen_unpack_mode.lsb_is_one)) || clr_q)
--------------------------1-------------------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T9,T28,T35 |
LINE 136
SUB-EXPRESSION (rready_i && (depth_q == gen_unpack_mode.lsb_is_one))
----1--- -------------------2-------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T9,T28,T35 |
| 1 | 0 | Covered | T9,T28,T35 |
| 1 | 1 | Covered | T9,T28,T35 |
LINE 136
SUB-EXPRESSION (depth_q == gen_unpack_mode.lsb_is_one)
-------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T9,T28,T35 |
LINE 137
EXPRESSION (((ClearOnRead && clear_status)) || clr_q)
---------------1--------------- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
LINE 138
EXPRESSION (wvalid_i && wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T4,T9,T28 |
LINE 139
EXPRESSION (rvalid_o && rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T4,T9,T28 |
| 1 | 1 | Covered | T9,T28,T35 |
LINE 141
EXPRESSION (clear_status ? '0 : (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 141
SUB-EXPRESSION (load_data ? gen_unpack_mode.max_value : (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q))
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T9,T28 |
LINE 141
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((depth_q - 1)) : depth_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T9,T28,T35 |
LINE 146
EXPRESSION (clear_status ? '0 : (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q))
------1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (gen_unpack_mode.pull_data ? ((gen_unpack_mode.ptr_q + 1)) : gen_unpack_mode.ptr_q)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T9,T28,T35 |
LINE 150
EXPRESSION (clear_data ? '0 : (load_data ? wdata_i : data_q))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 150
SUB-EXPRESSION (load_data ? wdata_i : data_q)
----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T4,T9,T28 |
LINE 155
EXPRESSION ((depth_q == '0) && ((!clr_q)))
-------1------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T9,T28 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 155
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 157
EXPRESSION (( ! (depth_q == '0) ) && ((!clr_q)))
----------1---------- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T95,T167,T180 |
| 1 | 1 | Covered | T4,T9,T28 |
LINE 157
SUB-EXPRESSION ( ! (depth_q == '0) )
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T9,T28 |
| 1 | Covered | T1,T2,T3 |
LINE 157
SUB-EXPRESSION (depth_q == '0)
-------1-------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
| Line No. | Total | Covered | Percent |
| Branches |
|
14 |
14 |
100.00 |
| TERNARY |
141 |
4 |
4 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
150 |
3 |
3 |
100.00 |
| IF |
81 |
2 |
2 |
100.00 |
| IF |
126 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_packer_fifo.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 141 (clear_status) ?
-2-: 141 (load_data) ?
-3-: 141 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T4,T9,T28 |
| 0 |
0 |
1 |
Covered |
T9,T28,T35 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 146 (clear_status) ?
-2-: 146 (gen_unpack_mode.pull_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T9,T28,T35 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 150 (clear_data) ?
-2-: 150 (load_data) ?
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T4,T9,T28 |
| 0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 81 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 126 if ((!rst_ni))
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_prim_packer_fifo_ep
Assertion Details
DataOStableWhenPending_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215450748 |
245813 |
0 |
800 |
| T4 |
1967 |
1062 |
0 |
1 |
| T5 |
2140 |
0 |
0 |
1 |
| T6 |
10289 |
0 |
0 |
1 |
| T9 |
1476 |
550 |
0 |
1 |
| T10 |
4848 |
0 |
0 |
1 |
| T22 |
1298 |
0 |
0 |
1 |
| T23 |
125123 |
0 |
0 |
1 |
| T26 |
2384 |
0 |
0 |
1 |
| T27 |
2199 |
0 |
0 |
1 |
| T28 |
0 |
1715 |
0 |
0 |
| T29 |
0 |
2191 |
0 |
0 |
| T30 |
0 |
1995 |
0 |
0 |
| T35 |
0 |
1365 |
0 |
0 |
| T36 |
0 |
2828 |
0 |
0 |
| T38 |
0 |
808 |
0 |
0 |
| T63 |
1205 |
0 |
0 |
1 |
| T95 |
0 |
217 |
0 |
0 |
| T174 |
0 |
1862 |
0 |
0 |
ValidOPairedWithReadyI_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215450748 |
245813 |
0 |
0 |
| T4 |
1967 |
1062 |
0 |
0 |
| T5 |
2140 |
0 |
0 |
0 |
| T6 |
10289 |
0 |
0 |
0 |
| T9 |
1476 |
550 |
0 |
0 |
| T10 |
4848 |
0 |
0 |
0 |
| T22 |
1298 |
0 |
0 |
0 |
| T23 |
125123 |
0 |
0 |
0 |
| T26 |
2384 |
0 |
0 |
0 |
| T27 |
2199 |
0 |
0 |
0 |
| T28 |
0 |
1715 |
0 |
0 |
| T29 |
0 |
2191 |
0 |
0 |
| T30 |
0 |
1995 |
0 |
0 |
| T35 |
0 |
1365 |
0 |
0 |
| T36 |
0 |
2828 |
0 |
0 |
| T38 |
0 |
808 |
0 |
0 |
| T63 |
1205 |
0 |
0 |
0 |
| T95 |
0 |
217 |
0 |
0 |
| T174 |
0 |
1862 |
0 |
0 |