Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	150	1			T3	1		T20	1		T37	1
auto_req_mode	128	1			T57	1		T58	1		T35	1
sw_mode	2791	1			T5	3		T21	5		T44	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

294

1

T3

1

T37

1

T28

1

single

95

1

T20

1

T32

1

T135

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1140	1			T3	1		T5	3		T44	1
auto[2]	47	1			T165	1		T200	9		T191	1
auto[3]	163	1			T20	1		T166	1		T164	1
auto[4]	154	1			T31	1		T54	1		T272	1
auto[5]	90	1			T273	1		T274	1		T186	36
auto[6]	81	1			T246	1		T275	1		T276	1
auto[7]	1394	1			T21	5		T22	40		T25	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	84	1			T3	1		T37	1		T28	1
auto[1]	auto_req_mode	75	1			T57	1		T58	1		T60	1
auto[1]	sw_mode	981	1			T5	3		T44	1		T119	1
auto[2]	boot_req_mode	4	1			T165	1		T277	1		T278	1
auto[2]	auto_req_mode	4	1			T191	1		T11	1		T279	1
auto[2]	sw_mode	39	1			T200	9		T280	1		T281	1
auto[3]	boot_req_mode	6	1			T20	1		T166	1		T282	1
auto[3]	auto_req_mode	2	1			T283	1		T284	1		-	-
auto[3]	sw_mode	155	1			T164	1		T185	85		T187	67
auto[4]	boot_req_mode	1	1			T285	1		-	-		-	-
auto[4]	auto_req_mode	5	1			T272	1		T286	1		T287	1
auto[4]	sw_mode	148	1			T31	1		T54	1		T184	48
auto[5]	boot_req_mode	3	1			T274	1		T288	1		T289	1
auto[5]	auto_req_mode	2	1			T273	1		T290	1		-	-
auto[5]	sw_mode	85	1			T186	36		T291	22		T292	6
auto[6]	boot_req_mode	5	1			T293	1		T294	1		T295	1
auto[6]	auto_req_mode	4	1			T276	1		T296	1		T297	1
auto[6]	sw_mode	72	1			T246	1		T275	1		T298	1
auto[7]	boot_req_mode	47	1			T25	1		T26	1		T27	1
auto[7]	auto_req_mode	36	1			T35	1		T75	1		T173	1
auto[7]	sw_mode	1311	1			T21	5		T22	40		T118	5