Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	613794	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5006472

1

T1

21

T2

21

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1487851	1			T1	33		T2	44		T3	1
values[0x0]	1909484	1			T1	15		T2	13		T3	3
values[0x1]	2222931	1			T1	7		T2	8		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	303625	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5316641

1

T1

29

T2

32

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	21474	1			T21	3		T37	3		T22	578
valid_sources[0x01]	22051	1			T21	3		T44	2		T22	508
valid_sources[0x02]	21907	1			T6	1		T21	1		T22	454
valid_sources[0x03]	23171	1			T2	1		T21	3		T22	500
valid_sources[0x04]	22137	1			T37	2		T22	502		T120	6
valid_sources[0x05]	21467	1			T21	3		T37	5		T22	505
valid_sources[0x06]	22309	1			T21	1		T22	475		T120	4
valid_sources[0x07]	21996	1			T2	1		T37	3		T22	544
valid_sources[0x08]	21748	1			T21	3		T22	515		T120	1
valid_sources[0x09]	21663	1			T2	1		T38	2		T22	516
valid_sources[0x0a]	21844	1			T21	1		T22	461		T120	3
valid_sources[0x0b]	21106	1			T1	2		T2	1		T22	496
valid_sources[0x0c]	22254	1			T21	1		T37	2		T22	513
valid_sources[0x0d]	21966	1			T44	2		T22	487		T120	3
valid_sources[0x0e]	21348	1			T21	4		T22	511		T120	3
valid_sources[0x0f]	21932	1			T44	1		T22	507		T25	1
valid_sources[0x10]	22127	1			T4	3		T21	1		T44	1
valid_sources[0x11]	21461	1			T44	1		T22	504		T25	5
valid_sources[0x12]	22160	1			T6	7		T44	1		T22	526
valid_sources[0x13]	21448	1			T1	1		T22	500		T120	2
valid_sources[0x14]	23133	1			T37	1		T22	522		T25	2
valid_sources[0x15]	21417	1			T21	1		T37	1		T22	467
valid_sources[0x16]	22001	1			T21	1		T44	1		T37	1
valid_sources[0x17]	21712	1			T7	15		T22	477		T25	2
valid_sources[0x18]	21740	1			T22	535		T120	11		T23	783
valid_sources[0x19]	22881	1			T38	1		T21	2		T22	508
valid_sources[0x1a]	21985	1			T22	484		T120	2		T23	791
valid_sources[0x1b]	21892	1			T1	1		T2	1		T21	1
valid_sources[0x1c]	21120	1			T22	484		T120	7		T23	798
valid_sources[0x1d]	22738	1			T21	1		T22	439		T120	4
valid_sources[0x1e]	21638	1			T1	1		T21	3		T22	464
valid_sources[0x1f]	20799	1			T44	1		T22	471		T25	4
valid_sources[0x20]	20060	1			T21	1		T22	494		T120	3
valid_sources[0x21]	21403	1			T21	1		T22	498		T120	3
valid_sources[0x22]	22432	1			T2	1		T21	4		T22	467
valid_sources[0x23]	22273	1			T1	1		T19	1		T22	501
valid_sources[0x24]	22710	1			T21	4		T22	490		T120	3
valid_sources[0x25]	22142	1			T2	1		T21	1		T22	453
valid_sources[0x26]	22369	1			T21	1		T22	506		T120	1
valid_sources[0x27]	21738	1			T21	2		T44	1		T22	535
valid_sources[0x28]	22205	1			T21	2		T22	519		T120	4
valid_sources[0x29]	21077	1			T21	1		T37	2		T22	487
valid_sources[0x2a]	20363	1			T21	1		T22	488		T120	5
valid_sources[0x2b]	21542	1			T21	1		T22	489		T120	6
valid_sources[0x2c]	21653	1			T21	1		T22	482		T120	13
valid_sources[0x2d]	21500	1			T22	452		T14	1		T120	1
valid_sources[0x2e]	22405	1			T21	2		T37	1		T22	500
valid_sources[0x2f]	21680	1			T1	1		T21	3		T44	1
valid_sources[0x30]	20428	1			T22	462		T120	3		T23	780
valid_sources[0x31]	21651	1			T22	509		T120	1		T23	786
valid_sources[0x32]	22195	1			T21	3		T22	527		T14	1
valid_sources[0x33]	22687	1			T2	2		T21	1		T19	1
valid_sources[0x34]	22019	1			T1	1		T22	451		T120	2
valid_sources[0x35]	20933	1			T21	2		T19	1		T22	503
valid_sources[0x36]	22061	1			T1	1		T2	3		T21	4
valid_sources[0x37]	21285	1			T21	2		T22	510		T120	4
valid_sources[0x38]	22413	1			T22	527		T25	4		T120	2
valid_sources[0x39]	22200	1			T21	2		T44	1		T22	503
valid_sources[0x3a]	22447	1			T7	8		T22	520		T25	2
valid_sources[0x3b]	21646	1			T38	2		T22	451		T120	3
valid_sources[0x3c]	21149	1			T2	1		T21	1		T22	485
valid_sources[0x3d]	21732	1			T37	2		T22	455		T120	2
valid_sources[0x3e]	21881	1			T1	1		T21	2		T22	471
valid_sources[0x3f]	21289	1			T5	168		T44	1		T22	522
valid_sources[0x40]	22094	1			T22	516		T120	2		T23	778
valid_sources[0x41]	21494	1			T21	1		T37	3		T22	469
valid_sources[0x42]	21641	1			T21	1		T22	484		T120	4
valid_sources[0x43]	22633	1			T37	1		T22	525		T25	9
valid_sources[0x44]	22997	1			T21	1		T22	502		T120	3
valid_sources[0x45]	21900	1			T21	1		T37	3		T22	465
valid_sources[0x46]	21957	1			T2	1		T22	465		T120	2
valid_sources[0x47]	21573	1			T21	1		T37	1		T22	503
valid_sources[0x48]	22377	1			T21	3		T22	509		T121	2
valid_sources[0x49]	22009	1			T38	1		T21	1		T22	522
valid_sources[0x4a]	21598	1			T4	1		T21	2		T37	1
valid_sources[0x4b]	21794	1			T21	1		T22	482		T25	4
valid_sources[0x4c]	21406	1			T21	1		T22	527		T120	4
valid_sources[0x4d]	22772	1			T21	3		T22	523		T120	1
valid_sources[0x4e]	21438	1			T21	3		T37	1		T22	498
valid_sources[0x4f]	21612	1			T2	2		T22	522		T119	47
valid_sources[0x50]	23104	1			T21	2		T22	506		T120	3
valid_sources[0x51]	21773	1			T2	1		T21	1		T19	2
valid_sources[0x52]	21421	1			T1	3		T6	4		T21	5
valid_sources[0x53]	21855	1			T2	1		T4	1		T22	543
valid_sources[0x54]	22248	1			T21	6		T37	1		T22	511
valid_sources[0x55]	21633	1			T2	2		T21	2		T7	9
valid_sources[0x56]	21685	1			T21	1		T22	554		T120	1
valid_sources[0x57]	21583	1			T22	482		T120	2		T23	831
valid_sources[0x58]	21873	1			T21	1		T44	1		T22	503
valid_sources[0x59]	22205	1			T37	1		T22	486		T120	1
valid_sources[0x5a]	21629	1			T1	1		T2	1		T4	1
valid_sources[0x5b]	22739	1			T21	1		T22	464		T120	1
valid_sources[0x5c]	22230	1			T21	1		T22	495		T120	3
valid_sources[0x5d]	22120	1			T6	5		T21	2		T22	480
valid_sources[0x5e]	20699	1			T22	521		T120	1		T23	878
valid_sources[0x5f]	21741	1			T21	1		T22	509		T25	1
valid_sources[0x60]	21388	1			T1	2		T22	506		T120	4
valid_sources[0x61]	22502	1			T21	1		T44	3		T22	473
valid_sources[0x62]	22020	1			T21	1		T44	1		T22	482
valid_sources[0x63]	22033	1			T22	537		T25	7		T120	1
valid_sources[0x64]	22753	1			T21	1		T37	2		T22	517
valid_sources[0x65]	21774	1			T1	1		T2	1		T19	1
valid_sources[0x66]	21298	1			T4	1		T44	1		T22	528
valid_sources[0x67]	21685	1			T22	516		T120	4		T23	877
valid_sources[0x68]	23018	1			T1	1		T4	2		T22	492
valid_sources[0x69]	21115	1			T2	1		T21	1		T22	518
valid_sources[0x6a]	21360	1			T44	2		T37	2		T22	537
valid_sources[0x6b]	21720	1			T2	2		T21	1		T22	486
valid_sources[0x6c]	21668	1			T21	1		T22	489		T120	1
valid_sources[0x6d]	21606	1			T21	2		T44	1		T22	506
valid_sources[0x6e]	22214	1			T4	5		T22	509		T25	1
valid_sources[0x6f]	21711	1			T1	1		T21	1		T22	504
valid_sources[0x70]	21483	1			T21	1		T22	523		T25	4
valid_sources[0x71]	22021	1			T22	505		T25	3		T120	5
valid_sources[0x72]	22930	1			T21	1		T22	516		T120	9
valid_sources[0x73]	21500	1			T21	1		T44	1		T37	1
valid_sources[0x74]	20948	1			T1	1		T21	3		T22	529
valid_sources[0x75]	21532	1			T44	1		T22	495		T120	3
valid_sources[0x76]	21912	1			T2	1		T21	1		T22	487
valid_sources[0x77]	21842	1			T1	1		T21	1		T22	513
valid_sources[0x78]	21322	1			T21	4		T44	3		T22	471
valid_sources[0x79]	21278	1			T21	1		T19	1		T37	1
valid_sources[0x7a]	23711	1			T2	1		T21	2		T22	517
valid_sources[0x7b]	22306	1			T1	1		T21	2		T22	487
valid_sources[0x7c]	21123	1			T2	1		T21	1		T44	3
valid_sources[0x7d]	22667	1			T21	1		T44	1		T22	544
valid_sources[0x7e]	20848	1			T4	5		T21	1		T44	1
valid_sources[0x7f]	22028	1			T1	1		T22	476		T120	5
valid_sources[0x80]	22574	1			T1	1		T20	329		T21	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1263582

1

T1

9

T2

10

T3

1

values[0x0]

all_enables

biggest_size

1870337

1

T1

8

T2

8

T3

1

values[0x1]

all_enables

biggest_size

1872553

1

T1

4

T2

3

T3

1