Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
67.19	67.19	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	67.19	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
67.19	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	21	31	59.62

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	21	31	59.62	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2388	1			T20	2		T21	5		T37	1
non_zero_bins[1]	1737	1			T20	1		T22	11		T25	1
zero	8172	1			T1	8		T2	5		T3	3

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	473	1			T22	4		T118	1		T119	1
uni	3445	1			T1	1		T20	3		T5	3
gen	3663	1			T1	4		T2	3		T3	1
res	753	1			T21	1		T22	5		T120	2
ins	3963	1			T1	3		T2	2		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8398

1

T1

5

T2

2

T3

3

mubi_true

3899

1

T1

3

T2

3

T20

4

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

50

1

T1

1

T2

1

T13

1

pass

12247

1

T1

7

T2

4

T3

3

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	21	31	59.62	21
Automatically Generated Cross Bins	52	21	31	59.62	21
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	4

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	100	1			T22	2		T119	1		T23	3
upd	non_zero_bins[0]	pass	mubi_true	101	1			T22	1		T23	1		T194	1
upd	non_zero_bins[1]	pass	mubi_false	74	1			T118	1		T24	2		T179	1
upd	non_zero_bins[1]	pass	mubi_true	84	1			T23	2		T24	1		T133	2
upd	zero	pass	mubi_false	69	1			T26	1		T200	1		T133	2
upd	zero	pass	mubi_true	45	1			T22	1		T120	1		T133	2
uni	zero	fail	mubi_false	8	1			T110	1		T111	1		T112	1
uni	zero	pass	mubi_false	2526	1			T1	1		T20	2		T21	4
uni	zero	pass	mubi_true	911	1			T20	1		T5	3		T21	2
gen	non_zero_bins[0]	pass	mubi_false	401	1			T22	6		T119	1		T23	4
gen	non_zero_bins[0]	pass	mubi_true	456	1			T20	1		T21	1		T22	6
gen	non_zero_bins[1]	pass	mubi_false	309	1			T22	1		T120	1		T23	3
gen	non_zero_bins[1]	pass	mubi_true	306	1			T22	2		T118	2		T23	4
gen	zero	fail	mubi_false	30	1			T1	1		T2	1		T13	1
gen	zero	pass	mubi_false	1769	1			T1	1		T3	1		T4	1
gen	zero	pass	mubi_true	392	1			T1	2		T2	2		T21	1
res	non_zero_bins[0]	pass	mubi_false	169	1			T24	4		T57	2		T58	2
res	non_zero_bins[0]	pass	mubi_true	154	1			T21	1		T22	3		T23	4
res	non_zero_bins[1]	pass	mubi_false	134	1			T120	2		T23	1		T24	2
res	non_zero_bins[1]	pass	mubi_true	148	1			T22	2		T23	3		T24	2
res	zero	fail	mubi_false	8	1			T63	1		T238	1		T239	1
res	zero	pass	mubi_false	75	1			T23	2		T24	2		T27	1
res	zero	pass	mubi_true	65	1			T24	1		T192	1		T179	1
ins	non_zero_bins[0]	pass	mubi_false	519	1			T21	2		T37	1		T22	5
ins	non_zero_bins[0]	pass	mubi_true	488	1			T20	1		T21	1		T22	7
ins	non_zero_bins[1]	pass	mubi_false	339	1			T22	2		T25	1		T120	2
ins	non_zero_bins[1]	pass	mubi_true	343	1			T20	1		T22	4		T118	1
ins	zero	fail	mubi_false	3	1			T92	1		T93	1		T240	1
ins	zero	fail	mubi_true	1	1			T94	1		-	-		-	-
ins	zero	pass	mubi_false	1865	1			T1	2		T2	1		T3	2
ins	zero	pass	mubi_true	405	1			T1	1		T2	1		T37	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded