Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	208234431	8866055	0	0
boot_gen_cmd_rd_A	208234431	73521	0	0
boot_ins_cmd_rd_A	208234431	84514	0	0
ctrl_rd_A	208234431	73555	0	0
err_code_test_rd_A	208234431	83508	0	0
intr_enable_rd_A	208234431	79678	0	0
max_num_reqs_between_reseeds_rd_A	208234431	74160	0	0
regwen_rd_A	208234431	85203	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208234431	8866055	0	0
T8	1328	0	0	0
T14	565	0	0	0
T22	538482	215097	0	0
T23	0	342267	0	0
T24	0	225541	0	0
T25	5919	0	0	0
T28	1400	0	0	0
T29	1125	0	0	0
T118	14369	0	0	0
T119	1807	0	0	0
T120	26644	0	0	0
T121	1273	0	0	0
T133	0	141424	0	0
T178	0	83988	0	0
T179	0	57575	0	0
T180	0	104206	0	0
T181	0	177988	0	0
T182	0	105875	0	0
T183	0	142889	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208234431	73521	0	0
T10	1368	0	0	0
T77	3162	0	0	0
T90	1138	0	0	0
T111	2824	0	0	0
T127	1263	0	0	0
T133	376902	2316	0	0
T143	1303	0	0	0
T179	0	788	0	0
T183	0	4110	0	0
T184	0	2836	0	0
T185	0	7048	0	0
T186	0	1466	0	0
T187	0	3605	0	0
T188	0	5765	0	0
T189	0	11970	0	0
T190	0	3310	0	0
T191	1956	0	0	0
T192	18505	0	0	0
T193	1360	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208234431	84514	0	0
T10	1368	0	0	0
T77	3162	0	0	0
T90	1138	0	0	0
T111	2824	0	0	0
T127	1263	0	0	0
T133	376902	2510	0	0
T143	1303	0	0	0
T179	0	1055	0	0
T183	0	4744	0	0
T184	0	3437	0	0
T185	0	7857	0	0
T186	0	1606	0	0
T187	0	4672	0	0
T188	0	5915	0	0
T189	0	13388	0	0
T190	0	4034	0	0
T191	1956	0	0	0
T192	18505	0	0	0
T193	1360	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208234431	73555	0	0
T8	1328	0	0	0
T23	620512	0	0	0
T26	2435	0	0	0
T29	1125	0	0	0
T32	1162	0	0	0
T120	26644	4	0	0
T121	1273	0	0	0
T126	967	0	0	0
T133	0	2366	0	0
T134	2596	0	0	0
T166	2125	0	0	0
T179	0	822	0	0
T183	0	4261	0	0
T194	0	3	0	0
T195	0	1	0	0
T196	0	6	0	0
T197	0	2	0	0
T198	0	1	0	0
T199	0	2	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208234431	83508	0	0
T10	1368	0	0	0
T77	3162	0	0	0
T90	1138	0	0	0
T111	2824	0	0	0
T127	1263	0	0	0
T133	376902	2691	0	0
T143	1303	0	0	0
T179	0	963	0	0
T183	0	5059	0	0
T184	0	3123	0	0
T185	0	7733	0	0
T186	0	1515	0	0
T187	0	4234	0	0
T188	0	6062	0	0
T189	0	13443	0	0
T190	0	3972	0	0
T191	1956	0	0	0
T192	18505	0	0	0
T193	1360	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208234431	79678	0	0
T7	2688	0	0	0
T14	565	0	0	0
T19	1351	0	0	0
T21	11341	15	0	0
T22	538482	0	0	0
T25	5919	0	0	0
T28	1400	0	0	0
T37	2513	0	0	0
T44	1323	0	0	0
T118	14369	0	0	0
T120	0	131	0	0
T133	0	2650	0	0
T179	0	1028	0	0
T183	0	4138	0	0
T194	0	33	0	0
T195	0	56	0	0
T196	0	61	0	0
T198	0	70	0	0
T200	0	21	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208234431	74160	0	0
T10	1368	0	0	0
T77	3162	0	0	0
T90	1138	0	0	0
T111	2824	0	0	0
T127	1263	0	0	0
T133	376902	2458	0	0
T143	1303	0	0	0
T179	0	788	0	0
T183	0	4212	0	0
T184	0	3147	0	0
T185	0	6709	0	0
T186	0	1556	0	0
T187	0	4160	0	0
T188	0	5350	0	0
T189	0	11420	0	0
T190	0	3208	0	0
T191	1956	0	0	0
T192	18505	0	0	0
T193	1360	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208234431	85203	0	0
T10	1368	0	0	0
T77	3162	0	0	0
T90	1138	0	0	0
T111	2824	0	0	0
T127	1263	0	0	0
T133	376902	2579	0	0
T143	1303	0	0	0
T179	0	946	0	0
T183	0	4996	0	0
T184	0	3241	0	0
T185	0	7900	0	0
T186	0	1690	0	0
T187	0	4547	0	0
T188	0	5888	0	0
T189	0	13437	0	0
T190	0	3913	0	0
T191	1956	0	0	0
T192	18505	0	0	0
T193	1360	0	0	0