Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.40	100.00	100.00		72.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	94.40	100.00	100.00		72.00	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.40	100.00	100.00		72.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.40	100.00	100.00		72.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		106	106	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	102	102	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
77	1	1
78	1	1
81	1	1
82	1	1
			MISSING_ELSE
86	1	1
87	1	1
90	1	1
91	1	1
			MISSING_ELSE
95	1	1
98	1	1
99	1	1
			MISSING_ELSE
103	1	1
104	1	1
107	1	1
108	1	1
109	1	1
			MISSING_ELSE
114	1	1
115	1	1
116	1	1
			MISSING_ELSE
120	1	1
121	1	1
122	1	1
			MISSING_ELSE
126	1	1
127	1	1
128	1	1
			MISSING_ELSE
132	1	1
133	1	1
134	1	1
135	1	1
137	1	1
138	1	1
140	1	1
145	1	1
146	1	1
147	1	1
150	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
157	1	1
158	1	1
159	1	1
162	1	1
163	1	1
164	1	1
165	1	1
			MISSING_ELSE
169	1	1
172	1	1
175	1	1
183	1	1
184	1	1
186	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
207	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	14	14	100.00
Logical	14	14	100.00
Non-Logical	0	0
Event	0	0

 LINE       63
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T3,T19,T28
1	1	Covered	T1,T2,T3

 LINE       65
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T7,T8,T9
1	1	Covered	T7,T8,T9

 LINE       183
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T13
1	0	Covered	T4,T19,T7

 LINE       184
 EXPRESSION (local_escalate_i ? Error : RejectCsrngEntropy)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T13
1	Covered	T4,T19,T7

 LINE       197
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	75	54	72.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	153	Covered	T7,T8,T13
AutoCaptGenCnt	140	Covered	T7,T8,T13
AutoCaptReseedCnt	138	Covered	T8,T57,T58
AutoDispatch	122	Covered	T7,T8,T13
AutoFirstAckWait	116	Covered	T7,T8,T13
AutoLoadIns	68	Covered	T7,T8,T9
AutoSendGenCmd	147	Covered	T7,T8,T13
AutoSendReseedCmd	159	Covered	T57,T58,T35
BootDone	95	Covered	T1,T3,T20
BootGenAckWait	87	Covered	T1,T2,T3
BootInsAckWait	78	Covered	T1,T2,T3
BootLoadGen	82	Covered	T1,T2,T3
BootLoadIns	64	Covered	T1,T2,T3
BootLoadUni	99	Covered	T1,T20,T37
BootPulse	91	Covered	T1,T3,T20
BootUniAckWait	104	Covered	T1,T20,T37
Error	184	Covered	T4,T19,T7
Idle	109	Covered	T1,T2,T3
RejectCsrngEntropy	184	Covered	T1,T2,T13
SWPortMode	73	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	128	Covered	T8,T57,T58
AutoAckWait->Error	184	Covered	T59
AutoAckWait->Idle	207	Covered	T58,T60,T61
AutoAckWait->RejectCsrngEntropy	184	Covered	T13,T62,T63
AutoCaptGenCnt->AutoSendGenCmd	147	Covered	T7,T8,T13
AutoCaptGenCnt->Error	184	Covered	T64,T65,T66
AutoCaptGenCnt->Idle	207	Covered	T58,T67
AutoCaptGenCnt->RejectCsrngEntropy	184	Not Covered
AutoCaptReseedCnt->AutoSendReseedCmd	159	Covered	T57,T58,T35
AutoCaptReseedCnt->Error	184	Covered	T8,T68
AutoCaptReseedCnt->Idle	207	Covered	T69,T70,T71
AutoCaptReseedCnt->RejectCsrngEntropy	184	Not Covered
AutoDispatch->AutoCaptGenCnt	140	Covered	T7,T8,T13
AutoDispatch->AutoCaptReseedCnt	138	Covered	T8,T57,T58
AutoDispatch->Error	184	Covered	T72,T73,T74
AutoDispatch->Idle	135	Covered	T57,T35,T75
AutoDispatch->RejectCsrngEntropy	184	Not Covered
AutoFirstAckWait->AutoDispatch	122	Covered	T7,T8,T13
AutoFirstAckWait->Error	184	Covered	T56,T39,T76
AutoFirstAckWait->Idle	207	Covered	T77,T78,T79
AutoFirstAckWait->RejectCsrngEntropy	184	Not Covered
AutoLoadIns->AutoFirstAckWait	116	Covered	T7,T8,T13
AutoLoadIns->Error	184	Covered	T43,T80,T81
AutoLoadIns->Idle	207	Covered	T7,T8,T9
AutoLoadIns->RejectCsrngEntropy	184	Not Covered
AutoSendGenCmd->AutoAckWait	153	Covered	T7,T8,T13
AutoSendGenCmd->Error	184	Not Covered
AutoSendGenCmd->Idle	207	Not Covered
AutoSendGenCmd->RejectCsrngEntropy	184	Not Covered
AutoSendReseedCmd->AutoAckWait	165	Covered	T57,T58,T35
AutoSendReseedCmd->Error	184	Covered	T82
AutoSendReseedCmd->Idle	207	Covered	T83,T84
AutoSendReseedCmd->RejectCsrngEntropy	184	Not Covered
BootDone->BootLoadUni	99	Covered	T1,T20,T37
BootDone->Error	184	Covered	T85,T86,T87
BootDone->Idle	207	Covered	T29,T88,T89
BootDone->RejectCsrngEntropy	184	Not Covered
BootGenAckWait->BootPulse	91	Covered	T1,T3,T20
BootGenAckWait->Error	184	Covered	T14
BootGenAckWait->Idle	207	Covered	T15,T90,T41
BootGenAckWait->RejectCsrngEntropy	184	Covered	T1,T2,T51
BootInsAckWait->BootLoadGen	82	Covered	T1,T2,T3
BootInsAckWait->Error	184	Covered	T15,T41,T91
BootInsAckWait->Idle	207	Covered	T19,T28,T14
BootInsAckWait->RejectCsrngEntropy	184	Covered	T92,T93,T94
BootLoadGen->BootGenAckWait	87	Covered	T1,T2,T3
BootLoadGen->Error	184	Covered	T95,T96
BootLoadGen->Idle	207	Covered	T3,T97,T98
BootLoadGen->RejectCsrngEntropy	184	Not Covered
BootLoadIns->BootInsAckWait	78	Covered	T1,T2,T3
BootLoadIns->Error	184	Covered	T99,T100,T101
BootLoadIns->Idle	207	Covered	T102,T103,T104
BootLoadIns->RejectCsrngEntropy	184	Not Covered
BootLoadUni->BootUniAckWait	104	Covered	T1,T20,T37
BootLoadUni->Error	184	Not Covered
BootLoadUni->Idle	207	Not Covered
BootLoadUni->RejectCsrngEntropy	184	Not Covered
BootPulse->BootDone	95	Covered	T1,T3,T20
BootPulse->Error	184	Covered	T105,T106
BootPulse->Idle	207	Covered	T107,T108,T109
BootPulse->RejectCsrngEntropy	184	Not Covered
BootUniAckWait->Error	184	Not Covered
BootUniAckWait->Idle	109	Covered	T1,T20,T37
BootUniAckWait->RejectCsrngEntropy	184	Covered	T110,T111,T112
Error->RejectCsrngEntropy	184	Not Covered
Idle->AutoLoadIns	68	Covered	T7,T8,T9
Idle->BootLoadIns	64	Covered	T1,T2,T3
Idle->Error	184	Covered	T16,T17,T18
Idle->RejectCsrngEntropy	184	Not Covered
Idle->SWPortMode	73	Covered	T1,T2,T4
RejectCsrngEntropy->Error	184	Not Covered
RejectCsrngEntropy->Idle	207	Covered	T1,T2,T13
SWPortMode->Error	184	Covered	T4,T33,T40
SWPortMode->Idle	207	Covered	T1,T2,T5
SWPortMode->RejectCsrngEntropy	184	Not Covered

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
IF	42	2	2	100.00
CASE	61	35	35	100.00
IF	183	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	61	case (state_q)
-2-:	63	if ((boot_req_mode_i && edn_enable_i))
-3-:	65	if ((auto_req_mode_i && edn_enable_i))
-4-:	69	if (edn_enable_i)
-5-:	81	if (csrng_cmd_ack_i)
-6-:	90	if (csrng_cmd_ack_i)
-7-:	98	if ((!boot_req_mode_i))
-8-:	107	if (csrng_cmd_ack_i)
-9-:	115	if (sw_cmd_req_load_i)
-10-:	121	if (csrng_cmd_ack_i)
-11-:	127	if (csrng_cmd_ack_i)
-12-:	133	if ((!auto_req_mode_i))
-13-:	137	if (max_reqs_cnt_zero_i)
-14-:	152	if (cmd_sent_i)
-15-:	164	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T20
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T20,T37
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T3,T19
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T20,T37
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T1,T20,T37
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T20,T37
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T7,T8,T13
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T7,T8,T9
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T7,T8,T13
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T7,T8,T13
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T8,T13,T57
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T7,T8,T13
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T57,T35,T75
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T8,T57,T58
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T7,T8,T13
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T13
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T7,T8,T13
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T7,T8,T13
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T57,T58
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T57,T58,T35
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T57,T58,T35
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T13
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T19,T7
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T7,T9

	LineNo.	Expression
-1-:	183	if ((local_escalate_i || csrng_ack_err_i))
-2-:	184	(local_escalate_i) ? 
-3-:	197	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T4,T19,T7
1	0	-	Covered	T1,T2,T13
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	207683457	129469	0	0
FpvSecCmErrorStEscalate_A	207683457	130226	0	0
u_state_regs_A	207644931	207499196	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	129469	0	0
T4	890	383	0	0
T5	3744	0	0	0
T6	1673	0	0	0
T7	2688	1104	0	0
T8	0	401	0	0
T9	0	1030	0	0
T14	0	272	0	0
T15	0	469	0	0
T19	1351	713	0	0
T20	2742	0	0	0
T21	11341	0	0	0
T33	0	394	0	0
T37	2513	0	0	0
T38	1141	0	0	0
T39	0	1112	0	0
T44	1323	0	0	0
T56	0	650	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	130226	0	0
T4	890	384	0	0
T5	3744	0	0	0
T6	1673	0	0	0
T7	2688	1105	0	0
T8	0	402	0	0
T9	0	1031	0	0
T14	0	273	0	0
T15	0	470	0	0
T19	1351	714	0	0
T20	2742	0	0	0
T21	11341	0	0	0
T33	0	395	0	0
T37	2513	0	0	0
T38	1141	0	0	0
T39	0	1113	0	0
T44	1323	0	0	0
T56	0	651	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207644931	207499196	0	0
T1	2473	2418	0	0
T2	2160	2090	0	0
T3	1326	1264	0	0
T4	743	579	0	0
T5	3744	3629	0	0
T6	1673	1525	0	0
T19	1175	1011	0	0
T20	2742	2665	0	0
T21	11341	10704	0	0
T38	1141	1047	0	0