Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T4
DataWait	75	Covered	T1,T2,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T19,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T107,T108,T109
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T4
DataWait->AckPls	80	Covered	T1,T2,T4
DataWait->Disabled	107	Covered	T3,T28,T58
DataWait->Error	99	Covered	T7,T14,T15
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T6,T60,T143
EndPointClear->Error	99	Covered	T19,T9,T144
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T4
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T4,T7,T14

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T4
Idle	-	1	0	-	Covered	T1,T2,T4
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T4
DataWait	-	-	-	0	Covered	T2,T20,T5
AckPls	-	-	-	-	Covered	T1,T2,T4
Error	-	-	-	-	Covered	T4,T19,T7
default	-	-	-	-	Covered	T8,T56,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T19,T7
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1453784199	919383	0	0
FpvSecCmErrorStEscalate_A	1453784199	924682	0	0
u_state_regs_A	1453745673	1452725528	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1453784199	919383	0	0
T4	6230	2681	0	0
T5	26208	0	0	0
T6	11711	0	0	0
T7	18816	8078	0	0
T8	0	2757	0	0
T9	0	7560	0	0
T14	0	1904	0	0
T15	0	3283	0	0
T19	9457	5341	0	0
T20	19194	0	0	0
T21	79387	0	0	0
T33	0	2758	0	0
T37	17591	0	0	0
T38	7987	0	0	0
T39	0	7784	0	0
T44	9261	0	0	0
T56	0	4500	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1453784199	924682	0	0
T4	6230	2688	0	0
T5	26208	0	0	0
T6	11711	0	0	0
T7	18816	8085	0	0
T8	0	2764	0	0
T9	0	7567	0	0
T14	0	1911	0	0
T15	0	3290	0	0
T19	9457	5348	0	0
T20	19194	0	0	0
T21	79387	0	0	0
T33	0	2765	0	0
T37	17591	0	0	0
T38	7987	0	0	0
T39	0	7791	0	0
T44	9261	0	0	0
T56	0	4507	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1453745673	1452725528	0	0
T1	17311	16926	0	0
T2	15120	14630	0	0
T3	9282	8848	0	0
T4	6083	4935	0	0
T5	26208	25403	0	0
T6	11711	10675	0	0
T19	9281	8133	0	0
T20	19194	18655	0	0
T21	79387	74928	0	0
T38	7987	7329	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T20,T5
DataWait	75	Covered	T2,T20,T5
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T19,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T20,T5
DataWait->AckPls	80	Covered	T2,T20,T5
DataWait->Disabled	107	Covered	T61,T145,T146
DataWait->Error	99	Covered	T7,T14,T15
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T6,T60,T143
EndPointClear->Error	99	Covered	T19,T9,T144
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T20,T5
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T4,T33,T40

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T20,T5
Idle	-	1	0	-	Covered	T2,T20,T5
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T20,T5
DataWait	-	-	-	0	Covered	T2,T20,T5
AckPls	-	-	-	-	Covered	T2,T20,T5
Error	-	-	-	-	Covered	T4,T19,T7
default	-	-	-	-	Covered	T8,T56,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T19,T7
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	207683457	129669	0	0
FpvSecCmErrorStEscalate_A	207683457	130426	0	0
u_state_regs_A	207644931	207499196	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	129669	0	0
T4	890	383	0	0
T5	3744	0	0	0
T6	1673	0	0	0
T7	2688	1154	0	0
T8	0	351	0	0
T9	0	1080	0	0
T14	0	272	0	0
T15	0	469	0	0
T19	1351	763	0	0
T20	2742	0	0	0
T21	11341	0	0	0
T33	0	394	0	0
T37	2513	0	0	0
T38	1141	0	0	0
T39	0	1112	0	0
T44	1323	0	0	0
T56	0	600	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	130426	0	0
T4	890	384	0	0
T5	3744	0	0	0
T6	1673	0	0	0
T7	2688	1155	0	0
T8	0	352	0	0
T9	0	1081	0	0
T14	0	273	0	0
T15	0	470	0	0
T19	1351	764	0	0
T20	2742	0	0	0
T21	11341	0	0	0
T33	0	395	0	0
T37	2513	0	0	0
T38	1141	0	0	0
T39	0	1113	0	0
T44	1323	0	0	0
T56	0	601	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207644931	207499196	0	0
T1	2473	2418	0	0
T2	2160	2090	0	0
T3	1326	1264	0	0
T4	743	579	0	0
T5	3744	3629	0	0
T6	1673	1525	0	0
T19	1175	1011	0	0
T20	2742	2665	0	0
T21	11341	10704	0	0
T38	1141	1047	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T2,T4
DataWait	75	Covered	T1,T2,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T19,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T2,T4
DataWait->AckPls	80	Covered	T1,T2,T4
DataWait->Disabled	107	Covered	T147,T148
DataWait->Error	99	Covered	T56,T72,T149
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T6,T60,T143
EndPointClear->Error	99	Covered	T19,T9,T144
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T2,T4
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T4,T7,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T4
Idle	-	1	0	-	Covered	T1,T2,T4
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T4
DataWait	-	-	-	0	Covered	T20,T25,T134
AckPls	-	-	-	-	Covered	T1,T2,T4
Error	-	-	-	-	Covered	T4,T19,T7
default	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T19,T7
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	207683457	131619	0	0
FpvSecCmErrorStEscalate_A	207683457	132376	0	0
u_state_regs_A	207683457	207537722	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	131619	0	0
T4	890	383	0	0
T5	3744	0	0	0
T6	1673	0	0	0
T7	2688	1154	0	0
T8	0	401	0	0
T9	0	1080	0	0
T14	0	272	0	0
T15	0	469	0	0
T19	1351	763	0	0
T20	2742	0	0	0
T21	11341	0	0	0
T33	0	394	0	0
T37	2513	0	0	0
T38	1141	0	0	0
T39	0	1112	0	0
T44	1323	0	0	0
T56	0	650	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	132376	0	0
T4	890	384	0	0
T5	3744	0	0	0
T6	1673	0	0	0
T7	2688	1155	0	0
T8	0	402	0	0
T9	0	1081	0	0
T14	0	273	0	0
T15	0	470	0	0
T19	1351	764	0	0
T20	2742	0	0	0
T21	11341	0	0	0
T33	0	395	0	0
T37	2513	0	0	0
T38	1141	0	0	0
T39	0	1113	0	0
T44	1323	0	0	0
T56	0	651	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	207537722	0	0
T1	2473	2418	0	0
T2	2160	2090	0	0
T3	1326	1264	0	0
T4	890	726	0	0
T5	3744	3629	0	0
T6	1673	1525	0	0
T19	1351	1187	0	0
T20	2742	2665	0	0
T21	11341	10704	0	0
T38	1141	1047	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T20,T25,T8
DataWait	75	Covered	T20,T25,T8
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T19,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T20,T25,T8
DataWait->AckPls	80	Covered	T20,T25,T8
DataWait->Disabled	107	Covered	T67,T150
DataWait->Error	99	Covered	T151,T152,T153
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T6,T60,T143
EndPointClear->Error	99	Covered	T19,T9,T144
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T20,T25,T8
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T4,T7,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T20,T25,T8
Idle	-	1	0	-	Covered	T20,T25,T8
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T20,T25,T8
DataWait	-	-	-	0	Covered	T20,T25,T8
AckPls	-	-	-	-	Covered	T20,T25,T8
Error	-	-	-	-	Covered	T4,T19,T7
default	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T19,T7
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	207683457	131619	0	0
FpvSecCmErrorStEscalate_A	207683457	132376	0	0
u_state_regs_A	207683457	207537722	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	131619	0	0
T4	890	383	0	0
T5	3744	0	0	0
T6	1673	0	0	0
T7	2688	1154	0	0
T8	0	401	0	0
T9	0	1080	0	0
T14	0	272	0	0
T15	0	469	0	0
T19	1351	763	0	0
T20	2742	0	0	0
T21	11341	0	0	0
T33	0	394	0	0
T37	2513	0	0	0
T38	1141	0	0	0
T39	0	1112	0	0
T44	1323	0	0	0
T56	0	650	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	132376	0	0
T4	890	384	0	0
T5	3744	0	0	0
T6	1673	0	0	0
T7	2688	1155	0	0
T8	0	402	0	0
T9	0	1081	0	0
T14	0	273	0	0
T15	0	470	0	0
T19	1351	764	0	0
T20	2742	0	0	0
T21	11341	0	0	0
T33	0	395	0	0
T37	2513	0	0	0
T38	1141	0	0	0
T39	0	1113	0	0
T44	1323	0	0	0
T56	0	651	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	207537722	0	0
T1	2473	2418	0	0
T2	2160	2090	0	0
T3	1326	1264	0	0
T4	890	726	0	0
T5	3744	3629	0	0
T6	1673	1525	0	0
T19	1351	1187	0	0
T20	2742	2665	0	0
T21	11341	10704	0	0
T38	1141	1047	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T25,T26,T27
DataWait	75	Covered	T25,T26,T27
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T19,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T109
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T25,T26,T27
DataWait->AckPls	80	Covered	T25,T26,T27
DataWait->Disabled	107	Covered	T58,T154
DataWait->Error	99	Covered	T155,T105,T156
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T6,T60,T143
EndPointClear->Error	99	Covered	T19,T9,T144
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T25,T26,T27
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T4,T7,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T25,T26,T27
Idle	-	1	0	-	Covered	T25,T26,T27
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T25,T26,T27
DataWait	-	-	-	0	Covered	T25,T26,T27
AckPls	-	-	-	-	Covered	T25,T26,T27
Error	-	-	-	-	Covered	T4,T19,T7
default	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T19,T7
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	207683457	131619	0	0
FpvSecCmErrorStEscalate_A	207683457	132376	0	0
u_state_regs_A	207683457	207537722	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	131619	0	0
T4	890	383	0	0
T5	3744	0	0	0
T6	1673	0	0	0
T7	2688	1154	0	0
T8	0	401	0	0
T9	0	1080	0	0
T14	0	272	0	0
T15	0	469	0	0
T19	1351	763	0	0
T20	2742	0	0	0
T21	11341	0	0	0
T33	0	394	0	0
T37	2513	0	0	0
T38	1141	0	0	0
T39	0	1112	0	0
T44	1323	0	0	0
T56	0	650	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	132376	0	0
T4	890	384	0	0
T5	3744	0	0	0
T6	1673	0	0	0
T7	2688	1155	0	0
T8	0	402	0	0
T9	0	1081	0	0
T14	0	273	0	0
T15	0	470	0	0
T19	1351	764	0	0
T20	2742	0	0	0
T21	11341	0	0	0
T33	0	395	0	0
T37	2513	0	0	0
T38	1141	0	0	0
T39	0	1113	0	0
T44	1323	0	0	0
T56	0	651	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	207537722	0	0
T1	2473	2418	0	0
T2	2160	2090	0	0
T3	1326	1264	0	0
T4	890	726	0	0
T5	3744	3629	0	0
T6	1673	1525	0	0
T19	1351	1187	0	0
T20	2742	2665	0	0
T21	11341	10704	0	0
T38	1141	1047	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T28,T25,T26
DataWait	75	Covered	T28,T25,T26
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T19,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T108,T157
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T28,T25,T26
DataWait->AckPls	80	Covered	T28,T25,T26
DataWait->Disabled	107	Covered	T28,T158,T159
DataWait->Error	99	Covered	T80,T96,T73
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T6,T60,T143
EndPointClear->Error	99	Covered	T19,T9,T144
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T28,T25,T26
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T4,T7,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T28,T25,T26
Idle	-	1	0	-	Covered	T28,T25,T26
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T28,T25,T26
DataWait	-	-	-	0	Covered	T28,T25,T26
AckPls	-	-	-	-	Covered	T28,T25,T26
Error	-	-	-	-	Covered	T4,T19,T7
default	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T19,T7
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	207683457	131619	0	0
FpvSecCmErrorStEscalate_A	207683457	132376	0	0
u_state_regs_A	207683457	207537722	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	131619	0	0
T4	890	383	0	0
T5	3744	0	0	0
T6	1673	0	0	0
T7	2688	1154	0	0
T8	0	401	0	0
T9	0	1080	0	0
T14	0	272	0	0
T15	0	469	0	0
T19	1351	763	0	0
T20	2742	0	0	0
T21	11341	0	0	0
T33	0	394	0	0
T37	2513	0	0	0
T38	1141	0	0	0
T39	0	1112	0	0
T44	1323	0	0	0
T56	0	650	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	132376	0	0
T4	890	384	0	0
T5	3744	0	0	0
T6	1673	0	0	0
T7	2688	1155	0	0
T8	0	402	0	0
T9	0	1081	0	0
T14	0	273	0	0
T15	0	470	0	0
T19	1351	764	0	0
T20	2742	0	0	0
T21	11341	0	0	0
T33	0	395	0	0
T37	2513	0	0	0
T38	1141	0	0	0
T39	0	1113	0	0
T44	1323	0	0	0
T56	0	651	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	207537722	0	0
T1	2473	2418	0	0
T2	2160	2090	0	0
T3	1326	1264	0	0
T4	890	726	0	0
T5	3744	3629	0	0
T6	1673	1525	0	0
T19	1351	1187	0	0
T20	2742	2665	0	0
T21	11341	10704	0	0
T38	1141	1047	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T25,T29
DataWait	75	Covered	T1,T25,T29
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T19,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T107
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T25,T29
DataWait->AckPls	80	Covered	T1,T25,T29
DataWait->Disabled	107	Covered	T90
DataWait->Error	99	Covered	T160,T161
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T6,T60,T143
EndPointClear->Error	99	Covered	T19,T9,T144
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T25,T29
Idle->Disabled	107	Covered	T1,T2,T3
Idle->Error	99	Covered	T4,T7,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T25,T29
Idle	-	1	0	-	Covered	T1,T25,T29
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T25,T29
DataWait	-	-	-	0	Covered	T1,T25,T29
AckPls	-	-	-	-	Covered	T1,T25,T29
Error	-	-	-	-	Covered	T4,T19,T7
default	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T19,T7
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	207683457	131619	0	0
FpvSecCmErrorStEscalate_A	207683457	132376	0	0
u_state_regs_A	207683457	207537722	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	131619	0	0
T4	890	383	0	0
T5	3744	0	0	0
T6	1673	0	0	0
T7	2688	1154	0	0
T8	0	401	0	0
T9	0	1080	0	0
T14	0	272	0	0
T15	0	469	0	0
T19	1351	763	0	0
T20	2742	0	0	0
T21	11341	0	0	0
T33	0	394	0	0
T37	2513	0	0	0
T38	1141	0	0	0
T39	0	1112	0	0
T44	1323	0	0	0
T56	0	650	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	132376	0	0
T4	890	384	0	0
T5	3744	0	0	0
T6	1673	0	0	0
T7	2688	1155	0	0
T8	0	402	0	0
T9	0	1081	0	0
T14	0	273	0	0
T15	0	470	0	0
T19	1351	764	0	0
T20	2742	0	0	0
T21	11341	0	0	0
T33	0	395	0	0
T37	2513	0	0	0
T38	1141	0	0	0
T39	0	1113	0	0
T44	1323	0	0	0
T56	0	651	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	207537722	0	0
T1	2473	2418	0	0
T2	2160	2090	0	0
T3	1326	1264	0	0
T4	890	726	0	0
T5	3744	3629	0	0
T6	1673	1525	0	0
T19	1351	1187	0	0
T20	2742	2665	0	0
T21	11341	10704	0	0
T38	1141	1047	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T3,T25,T26
DataWait	75	Covered	T3,T25,T26
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T4,T19,T7
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T162
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T3,T25,T26
DataWait->AckPls	80	Covered	T3,T25,T26
DataWait->Disabled	107	Covered	T3,T97,T98
DataWait->Error	99	Covered	T163
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T16,T17,T18
EndPointClear->Disabled	107	Covered	T6,T60,T143
EndPointClear->Error	99	Covered	T19,T9,T144
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T3,T25,T26
Idle->Disabled	107	Covered	T1,T2,T5
Idle->Error	99	Covered	T4,T7,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T3,T25,T26
Idle	-	1	0	-	Covered	T3,T25,T26
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T3,T25,T26
DataWait	-	-	-	0	Covered	T3,T25,T26
AckPls	-	-	-	-	Covered	T3,T25,T26
Error	-	-	-	-	Covered	T4,T19,T7
default	-	-	-	-	Covered	T16,T17,T18

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T19,T7
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	207683457	131619	0	0
FpvSecCmErrorStEscalate_A	207683457	132376	0	0
u_state_regs_A	207683457	207537722	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	131619	0	0
T4	890	383	0	0
T5	3744	0	0	0
T6	1673	0	0	0
T7	2688	1154	0	0
T8	0	401	0	0
T9	0	1080	0	0
T14	0	272	0	0
T15	0	469	0	0
T19	1351	763	0	0
T20	2742	0	0	0
T21	11341	0	0	0
T33	0	394	0	0
T37	2513	0	0	0
T38	1141	0	0	0
T39	0	1112	0	0
T44	1323	0	0	0
T56	0	650	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	132376	0	0
T4	890	384	0	0
T5	3744	0	0	0
T6	1673	0	0	0
T7	2688	1155	0	0
T8	0	402	0	0
T9	0	1081	0	0
T14	0	273	0	0
T15	0	470	0	0
T19	1351	764	0	0
T20	2742	0	0	0
T21	11341	0	0	0
T33	0	395	0	0
T37	2513	0	0	0
T38	1141	0	0	0
T39	0	1113	0	0
T44	1323	0	0	0
T56	0	651	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	207537722	0	0
T1	2473	2418	0	0
T2	2160	2090	0	0
T3	1326	1264	0	0
T4	890	726	0	0
T5	3744	3629	0	0
T6	1673	1525	0	0
T19	1351	1187	0	0
T20	2742	2665	0	0
T21	11341	10704	0	0
T38	1141	1047	0	0