Group : tb.dut.u_edn_cov_if::edn_error_cg
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Group : tb.dut.u_edn_cov_if::edn_error_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
33.33 33.33 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_error_cg 33.33 1 100 1 64 64




Group Instance : edn_error_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
33.33 1 100 1 64 64




Summary for Group Instance edn_error_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 6 3 33.33


Variables for Group Instance edn_error_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_error_test 9 6 3 33.33 100 1 1 0


Summary for Variable cp_error_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 9 6 3 33.33


Automatically Generated Bins for cp_error_test

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[EdnSfifoRescmdErrTest] 0 1 1
auto[EdnSfifoGencmdErrTest] 0 1 1
auto[EdnSfifoOutputErrTest] 0 1 1
auto[EdnFifoWriteErrTest] 0 1 1
auto[EdnFifoReadErrTest] 0 1 1
auto[EdnFifoStateErrTest] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[EdnAckSmErrTest] 740 1 T4 1 T5 1 T7 1
auto[EdnMainSmErrTest] 740 1 T4 1 T5 1 T7 1
auto[EdnCntrErrTest] 37 1 T16 1 T38 1 T39 1

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