Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	647489	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5411720

1

T1

22

T2

17

T3

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1587136	1			T1	114		T2	46		T3	57
values[0x0]	2067386	1			T1	9		T2	9		T3	8
values[0x1]	2404687	1			T1	11		T2	8		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	315362	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5743847

1

T1

59

T2

32

T3

35

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23023	1			T9	1		T6	618		T36	2
valid_sources[0x01]	22533	1			T2	1		T6	124		T35	1
valid_sources[0x02]	22993	1			T1	2		T17	1		T6	529
valid_sources[0x03]	23362	1			T6	402		T35	1		T36	2
valid_sources[0x04]	25034	1			T1	3		T6	177		T35	2
valid_sources[0x05]	23855	1			T3	3		T4	1		T6	871
valid_sources[0x06]	25237	1			T1	1		T2	1		T17	1
valid_sources[0x07]	23253	1			T9	1		T6	156		T35	2
valid_sources[0x08]	23866	1			T1	1		T3	2		T9	1
valid_sources[0x09]	23739	1			T1	1		T6	220		T35	4
valid_sources[0x0a]	23993	1			T2	1		T4	1		T6	510
valid_sources[0x0b]	24554	1			T4	1		T6	1183		T35	1
valid_sources[0x0c]	24703	1			T3	1		T9	3		T6	1090
valid_sources[0x0d]	23108	1			T1	1		T9	1		T17	1
valid_sources[0x0e]	24291	1			T17	1		T4	1		T6	133
valid_sources[0x0f]	24229	1			T1	2		T6	590		T35	3
valid_sources[0x10]	23865	1			T3	1		T6	478		T35	1
valid_sources[0x11]	22555	1			T9	2		T6	294		T35	2
valid_sources[0x12]	22982	1			T17	1		T6	116		T35	1
valid_sources[0x13]	24654	1			T3	1		T9	3		T4	1
valid_sources[0x14]	22610	1			T2	1		T3	2		T6	281
valid_sources[0x15]	23116	1			T1	1		T4	1		T6	481
valid_sources[0x16]	25805	1			T3	2		T17	1		T6	740
valid_sources[0x17]	25148	1			T6	1558		T35	2		T36	4
valid_sources[0x18]	23118	1			T6	539		T36	1		T23	312
valid_sources[0x19]	23775	1			T1	1		T6	837		T35	2
valid_sources[0x1a]	23402	1			T1	2		T3	1		T6	205
valid_sources[0x1b]	23507	1			T1	1		T6	701		T35	2
valid_sources[0x1c]	22951	1			T6	193		T36	3		T23	312
valid_sources[0x1d]	23429	1			T9	1		T6	141		T35	2
valid_sources[0x1e]	24110	1			T6	715		T35	1		T36	1
valid_sources[0x1f]	22702	1			T1	1		T6	789		T35	2
valid_sources[0x20]	24542	1			T2	1		T6	1109		T35	2
valid_sources[0x21]	24652	1			T6	1199		T36	3		T13	1
valid_sources[0x22]	22426	1			T1	1		T4	1		T6	150
valid_sources[0x23]	23753	1			T2	1		T6	250		T35	3
valid_sources[0x24]	23004	1			T2	1		T6	501		T35	1
valid_sources[0x25]	23054	1			T1	1		T6	363		T36	1
valid_sources[0x26]	23486	1			T1	2		T2	1		T9	1
valid_sources[0x27]	24633	1			T6	992		T35	2		T36	2
valid_sources[0x28]	23876	1			T3	1		T9	1		T17	1
valid_sources[0x29]	22630	1			T2	2		T3	1		T9	3
valid_sources[0x2a]	22262	1			T2	1		T17	1		T6	3
valid_sources[0x2b]	24584	1			T9	1		T6	694		T35	3
valid_sources[0x2c]	23933	1			T1	1		T3	1		T9	2
valid_sources[0x2d]	23280	1			T2	1		T6	771		T35	1
valid_sources[0x2e]	23427	1			T6	252		T35	3		T36	2
valid_sources[0x2f]	24387	1			T3	2		T6	428		T23	300
valid_sources[0x30]	24196	1			T1	2		T3	4		T4	1
valid_sources[0x31]	24241	1			T6	588		T35	1		T13	1
valid_sources[0x32]	23288	1			T1	1		T3	1		T6	331
valid_sources[0x33]	24135	1			T1	2		T9	2		T6	681
valid_sources[0x34]	24315	1			T6	331		T35	2		T13	1
valid_sources[0x35]	23017	1			T1	2		T9	1		T6	274
valid_sources[0x36]	23500	1			T1	2		T9	1		T6	1173
valid_sources[0x37]	23686	1			T1	2		T2	1		T9	4
valid_sources[0x38]	24585	1			T1	2		T6	372		T35	3
valid_sources[0x39]	22884	1			T1	1		T17	1		T6	264
valid_sources[0x3a]	23081	1			T3	1		T4	3		T6	356
valid_sources[0x3b]	23479	1			T9	1		T17	1		T6	204
valid_sources[0x3c]	24352	1			T1	1		T6	140		T35	1
valid_sources[0x3d]	24666	1			T17	1		T6	514		T35	1
valid_sources[0x3e]	24931	1			T1	1		T9	2		T6	1244
valid_sources[0x3f]	23695	1			T2	1		T4	1		T6	141
valid_sources[0x40]	22753	1			T1	1		T17	1		T6	297
valid_sources[0x41]	25117	1			T9	1		T6	399		T35	1
valid_sources[0x42]	24122	1			T1	1		T2	1		T3	1
valid_sources[0x43]	23559	1			T1	1		T9	1		T6	182
valid_sources[0x44]	23120	1			T9	1		T4	1		T6	471
valid_sources[0x45]	23112	1			T1	1		T3	2		T6	569
valid_sources[0x46]	23019	1			T1	1		T6	150		T35	3
valid_sources[0x47]	24087	1			T6	188		T36	4		T13	2
valid_sources[0x48]	23685	1			T9	1		T6	511		T35	1
valid_sources[0x49]	23802	1			T9	1		T17	1		T6	414
valid_sources[0x4a]	22064	1			T6	371		T35	1		T36	3
valid_sources[0x4b]	23847	1			T2	1		T9	1		T6	291
valid_sources[0x4c]	23447	1			T17	1		T6	505		T36	4
valid_sources[0x4d]	23564	1			T6	742		T35	2		T36	2
valid_sources[0x4e]	23731	1			T1	1		T2	2		T9	1
valid_sources[0x4f]	24001	1			T6	139		T35	3		T36	1
valid_sources[0x50]	23644	1			T6	398		T35	1		T36	2
valid_sources[0x51]	21831	1			T1	1		T2	1		T9	1
valid_sources[0x52]	23678	1			T6	311		T35	4		T36	1
valid_sources[0x53]	23966	1			T1	1		T9	2		T6	383
valid_sources[0x54]	23688	1			T2	1		T6	332		T35	2
valid_sources[0x55]	23577	1			T1	1		T6	1011		T35	1
valid_sources[0x56]	24156	1			T9	1		T6	118		T35	2
valid_sources[0x57]	25263	1			T2	1		T6	487		T36	1
valid_sources[0x58]	24227	1			T1	1		T17	1		T6	282
valid_sources[0x59]	22377	1			T6	70		T36	1		T13	1
valid_sources[0x5a]	23232	1			T3	2		T6	170		T35	2
valid_sources[0x5b]	23202	1			T1	1		T2	2		T9	1
valid_sources[0x5c]	23410	1			T17	1		T4	1		T6	238
valid_sources[0x5d]	22845	1			T9	2		T6	257		T35	3
valid_sources[0x5e]	23466	1			T9	1		T6	340		T36	4
valid_sources[0x5f]	24610	1			T1	1		T9	1		T17	1
valid_sources[0x60]	23240	1			T1	1		T4	3		T6	102
valid_sources[0x61]	24079	1			T4	2		T6	583		T35	1
valid_sources[0x62]	23471	1			T2	1		T6	193		T35	1
valid_sources[0x63]	23645	1			T9	1		T6	393		T35	1
valid_sources[0x64]	23400	1			T17	1		T4	1		T6	170
valid_sources[0x65]	24488	1			T1	1		T9	1		T4	1
valid_sources[0x66]	23841	1			T2	1		T3	1		T9	1
valid_sources[0x67]	23622	1			T2	1		T17	2		T6	534
valid_sources[0x68]	23540	1			T6	364		T35	1		T36	1
valid_sources[0x69]	22730	1			T1	1		T2	1		T9	1
valid_sources[0x6a]	23230	1			T6	305		T36	4		T23	331
valid_sources[0x6b]	24550	1			T1	1		T2	3		T17	1
valid_sources[0x6c]	24288	1			T2	1		T9	1		T6	159
valid_sources[0x6d]	23930	1			T1	1		T3	1		T9	1
valid_sources[0x6e]	24011	1			T1	3		T3	1		T9	1
valid_sources[0x6f]	22358	1			T1	1		T3	1		T6	367
valid_sources[0x70]	25184	1			T6	717		T35	1		T36	1
valid_sources[0x71]	23819	1			T1	1		T3	2		T17	1
valid_sources[0x72]	21706	1			T9	1		T4	3		T6	195
valid_sources[0x73]	23426	1			T1	1		T6	296		T35	2
valid_sources[0x74]	23629	1			T6	767		T35	2		T36	1
valid_sources[0x75]	23130	1			T1	1		T9	1		T6	463
valid_sources[0x76]	22656	1			T6	399		T35	1		T36	2
valid_sources[0x77]	23234	1			T1	2		T17	1		T6	321
valid_sources[0x78]	23161	1			T3	1		T6	565		T35	1
valid_sources[0x79]	23200	1			T1	1		T6	248		T35	3
valid_sources[0x7a]	23922	1			T1	1		T6	522		T35	2
valid_sources[0x7b]	24520	1			T3	1		T9	1		T6	942
valid_sources[0x7c]	24931	1			T6	253		T36	2		T23	319
valid_sources[0x7d]	23793	1			T2	1		T6	240		T35	1
valid_sources[0x7e]	24726	1			T9	2		T6	688		T35	6
valid_sources[0x7f]	23571	1			T9	1		T17	1		T6	486
valid_sources[0x80]	22828	1			T3	3		T6	335		T35	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1361887

1

T1

7

T2

3

T3

5

values[0x0]

all_enables

biggest_size

2025918

1

T1

7

T2

9

T3

7

values[0x1]

all_enables

biggest_size

2023915

1

T1

8

T2

5

T3

9