Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
67.19	67.19	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	67.19	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
67.19	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	21	31	59.62

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	21	31	59.62	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2409	1			T2	2		T3	1		T9	2
non_zero_bins[1]	1794	1			T9	3		T6	16		T25	2
zero	8312	1			T1	1		T2	2		T17	6

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	535	1			T6	6		T25	1		T35	1
uni	3513	1			T2	1		T17	1		T6	44
gen	3727	1			T2	1		T9	2		T17	3
res	736	1			T2	1		T9	2		T6	6
ins	4004	1			T1	1		T2	1		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8491

1

T1

1

T2

2

T3

1

mubi_true

4024

1

T2

2

T17

3

T6

41

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

50

1

T17

1

T18

1

T19

1

pass

12465

1

T1

1

T2

4

T3

1

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	21	31	59.62	21
Automatically Generated Cross Bins	52	21	31	59.62	21
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	4

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	131	1			T6	2		T25	1		T23	3
upd	non_zero_bins[0]	pass	mubi_true	119	1			T36	1		T23	1		T48	1
upd	non_zero_bins[1]	pass	mubi_false	74	1			T23	1		T24	2		T241	1
upd	non_zero_bins[1]	pass	mubi_true	89	1			T6	3		T35	1		T23	1
upd	zero	pass	mubi_false	64	1			T6	1		T36	1		T23	1
upd	zero	pass	mubi_true	58	1			T36	1		T24	1		T48	1
uni	zero	fail	mubi_false	11	1			T17	1		T125	1		T126	1
uni	zero	pass	mubi_false	2527	1			T2	1		T6	27		T25	2
uni	zero	pass	mubi_true	975	1			T6	17		T35	3		T36	3
gen	non_zero_bins[0]	pass	mubi_false	435	1			T9	2		T6	5		T35	1
gen	non_zero_bins[0]	pass	mubi_true	437	1			T6	5		T36	1		T23	3
gen	non_zero_bins[1]	pass	mubi_false	318	1			T6	1		T25	1		T13	1
gen	non_zero_bins[1]	pass	mubi_true	323	1			T6	3		T23	3		T24	1
gen	zero	fail	mubi_false	25	1			T18	1		T71	1		T72	1
gen	zero	pass	mubi_false	1800	1			T17	1		T6	23		T35	4
gen	zero	pass	mubi_true	389	1			T2	1		T17	2		T6	2
res	non_zero_bins[0]	pass	mubi_false	161	1			T2	1		T6	1		T142	1
res	non_zero_bins[0]	pass	mubi_true	158	1			T64	1		T11	2		T24	2
res	non_zero_bins[1]	pass	mubi_false	124	1			T9	2		T6	1		T23	2
res	non_zero_bins[1]	pass	mubi_true	111	1			T23	2		T24	1		T30	1
res	zero	fail	mubi_false	8	1			T152	1		T189	1		T242	1
res	zero	pass	mubi_false	92	1			T6	2		T23	1		T10	2
res	zero	pass	mubi_true	82	1			T6	2		T13	2		T23	1
ins	non_zero_bins[0]	pass	mubi_false	474	1			T3	1		T6	9		T35	1
ins	non_zero_bins[0]	pass	mubi_true	494	1			T2	1		T6	2		T36	3
ins	non_zero_bins[1]	pass	mubi_false	383	1			T9	1		T6	2		T23	5
ins	non_zero_bins[1]	pass	mubi_true	372	1			T6	6		T25	1		T13	1
ins	zero	fail	mubi_false	4	1			T111	1		T243	1		T244	1
ins	zero	fail	mubi_true	2	1			T19	1		T110	1		-	-
ins	zero	pass	mubi_false	1860	1			T1	1		T17	1		T4	1
ins	zero	pass	mubi_true	415	1			T17	1		T6	1		T25	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded