Group : csrng_agent_pkg::device_genbits_cg
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Group : csrng_agent_pkg::device_genbits_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
78.57 78.57 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
csrng_agent_pkg.csrng_device_genbits_cg 78.57 1 100 1 64 64




Group Instance : csrng_agent_pkg.csrng_device_genbits_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
78.57 1 100 1 64 64




Summary for Group Instance csrng_agent_pkg.csrng_device_genbits_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 3 5 62.50


Variables for Group Instance csrng_agent_pkg.csrng_device_genbits_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csrng_glen 4 0 4 100.00 100 1 1 0
csrng_sts 2 0 2 100.00 100 1 1 0


Crosses for Group Instance csrng_agent_pkg.csrng_device_genbits_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
csrng_genbits_cross 8 3 5 62.50 100 1 1 0


Summary for Variable csrng_glen

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for csrng_glen

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
glens[0] 2134 1 T17 3 T6 22 T25 2
glens[1] 31 1 T2 1 T245 1 T12 1
glens[2] 37 1 T13 1 T246 1 T247 4
glens[3] 24 1 T31 1 T190 1 T248 1



Summary for Variable csrng_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_sts

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fail 25 1 T18 1 T71 1 T72 1
pass 3702 1 T2 1 T9 2 T17 3



Summary for Cross csrng_genbits_cross

Samples crossed: csrng_glen csrng_sts
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 3 5 62.50 3


Automatically Generated Cross Bins for csrng_genbits_cross

Uncovered bins
csrng_glencsrng_stsCOUNTAT LEASTNUMBERSTATUS
[glens[1] , glens[2] , glens[3]] [fail] -- -- 3


Covered bins
csrng_glencsrng_stsCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
glens[0] fail 25 1 T18 1 T71 1 T72 1
glens[0] pass 2109 1 T17 3 T6 22 T25 2
glens[1] pass 31 1 T2 1 T245 1 T12 1
glens[2] pass 37 1 T13 1 T246 1 T247 4
glens[3] pass 24 1 T31 1 T190 1 T248 1

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