Group : dv_base_reg_pkg::mubi_cov#(4,32'h00000006,32'h00000009)::mubi_cg
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Group : dv_base_reg_pkg::mubi_cov#(4,32'h00000006,32'h00000009)::mubi_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

4 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst 100.00 1 100 1 64 64
mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable 100.00 1 100 1 64 64




Group Instance : mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.auto_req_mode
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.boot_req_mode
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.cmd_fifo_rst
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0



Group Instance : mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group Instance mubi4_cov_of_mubi4_cov_of_edn_reg_block.ctrl.edn_enable
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 6 0 6 100.00 100 1 1 0


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 3 1 T154 2 T254 1 - -
others[1] 9 1 T47 1 T153 2 T255 1
others[2] 8 1 T136 1 T111 2 T256 1
others[3] 4 1 T152 2 T257 1 T258 1
false 1914 1 T1 1 T2 1 T3 1
true 530 1 T9 1 T17 2 T4 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 8 1 T125 2 T135 1 T189 2
others[1] 6 1 T71 2 T259 2 T243 2
others[2] 8 1 T17 2 T207 1 T260 2
others[3] 14 1 T47 1 T72 2 T136 1
false 1974 1 T1 1 T2 1 T3 1
true 458 1 T17 1 T25 1 T27 5


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 6 1 T261 1 T110 1 T255 1
others[1] 6 1 T47 1 T136 1 T105 1
others[2] 1 1 T207 1 - - - -
others[3] 8 1 T18 1 T19 1 T135 1
false 1949 1 T1 1 T2 1 T3 1
true 498 1 T9 1 T17 3 T4 3


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 9 1 T103 2 T135 1 T262 2
others[1] 9 1 T151 2 T186 2 T263 1
others[2] 16 1 T264 2 T136 1 T256 1
others[3] 8 1 T47 1 T150 2 T257 1
false 985 1 T9 2 T17 6 T4 6
true 1441 1 T1 1 T2 1 T3 1

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