Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	232099587	9609078	0	0
boot_gen_cmd_rd_A	232099587	98139	0	0
boot_ins_cmd_rd_A	232099587	111441	0	0
ctrl_rd_A	232099587	96282	0	0
err_code_test_rd_A	232099587	112736	0	0
intr_enable_rd_A	232099587	106381	0	0
max_num_reqs_between_reseeds_rd_A	232099587	98036	0	0
regwen_rd_A	232099587	111907	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232099587	9609078	0	0
T6	494180	205809	0	0
T7	1283	0	0	0
T13	2027	0	0	0
T23	234887	130783	0	0
T24	0	102688	0	0
T25	2859	0	0	0
T26	5120	0	0	0
T27	406	0	0	0
T33	1143	0	0	0
T35	14733	0	0	0
T36	17048	0	0	0
T48	0	147813	0	0
T141	0	61940	0	0
T145	0	164591	0	0
T146	0	177817	0	0
T149	0	56151	0	0
T195	0	149528	0	0
T196	0	186610	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232099587	98139	0	0
T38	392	0	0	0
T63	498	0	0	0
T68	3183	0	0	0
T97	896	0	0	0
T109	439	0	0	0
T141	174712	1870	0	0
T145	0	4312	0	0
T149	998002	0	0	0
T181	3380	0	0	0
T197	0	3062	0	0
T198	0	6954	0	0
T199	0	636	0	0
T200	0	4864	0	0
T201	0	7678	0	0
T202	0	2384	0	0
T203	0	4694	0	0
T204	0	2096	0	0
T205	3495	0	0	0
T206	3033	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232099587	111441	0	0
T38	392	0	0	0
T63	498	0	0	0
T68	3183	0	0	0
T97	896	0	0	0
T109	439	0	0	0
T141	174712	1995	0	0
T145	0	5250	0	0
T149	998002	0	0	0
T181	3380	0	0	0
T197	0	3345	0	0
T198	0	7659	0	0
T199	0	734	0	0
T200	0	5330	0	0
T201	0	9004	0	0
T202	0	3023	0	0
T203	0	4744	0	0
T204	0	2161	0	0
T205	3495	0	0	0
T206	3033	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232099587	96282	0	0
T10	3444	0	0	0
T11	2098	0	0	0
T24	253855	0	0	0
T31	2491	0	0	0
T34	1690	0	0	0
T47	0	6	0	0
T64	2769	6	0	0
T141	0	1894	0	0
T143	1157	0	0	0
T145	0	4667	0	0
T147	3135	0	0	0
T180	1660	0	0	0
T197	0	3053	0	0
T198	0	6428	0	0
T199	0	609	0	0
T200	0	4700	0	0
T201	0	7952	0	0
T207	0	3	0	0
T208	1293	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232099587	112736	0	0
T38	392	0	0	0
T63	498	0	0	0
T68	3183	0	0	0
T97	896	0	0	0
T109	439	0	0	0
T141	174712	1929	0	0
T145	0	5488	0	0
T149	998002	0	0	0
T181	3380	0	0	0
T197	0	3292	0	0
T198	0	7111	0	0
T199	0	802	0	0
T200	0	5155	0	0
T201	0	9549	0	0
T202	0	2955	0	0
T203	0	4927	0	0
T204	0	2407	0	0
T205	3495	0	0	0
T206	3033	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232099587	106381	0	0
T10	3444	0	0	0
T13	2027	0	0	0
T23	234887	0	0	0
T27	406	0	0	0
T31	2491	0	0	0
T36	17048	105	0	0
T45	0	52	0	0
T64	2769	0	0	0
T141	0	1882	0	0
T145	0	5238	0	0
T147	3135	0	0	0
T148	0	16	0	0
T179	1874	0	0	0
T180	1660	0	0	0
T197	0	3609	0	0
T209	0	32	0	0
T210	0	44	0	0
T211	0	90	0	0
T212	0	92	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232099587	98036	0	0
T38	392	0	0	0
T63	498	0	0	0
T68	3183	0	0	0
T97	896	0	0	0
T109	439	0	0	0
T141	174712	1854	0	0
T145	0	4452	0	0
T149	998002	0	0	0
T181	3380	0	0	0
T197	0	2980	0	0
T198	0	6535	0	0
T199	0	631	0	0
T200	0	4635	0	0
T201	0	7958	0	0
T202	0	2467	0	0
T203	0	4484	0	0
T204	0	2059	0	0
T205	3495	0	0	0
T206	3033	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	232099587	111907	0	0
T38	392	0	0	0
T63	498	0	0	0
T68	3183	0	0	0
T97	896	0	0	0
T109	439	0	0	0
T141	174712	2100	0	0
T145	0	5073	0	0
T149	998002	0	0	0
T181	3380	0	0	0
T197	0	3812	0	0
T198	0	7644	0	0
T199	0	694	0	0
T200	0	5652	0	0
T201	0	8742	0	0
T202	0	2865	0	0
T203	0	5344	0	0
T204	0	2097	0	0
T205	3495	0	0	0
T206	3033	0	0	0