Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	93.75	100.00	75.00			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	95.31	100.00	81.25			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.22	100.00	88.89			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.41	100.00	89.63			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.41	100.00	89.63			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T17,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T17,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T127,T128,T129
1	1	0	Not Covered
1	1	1	Covered	T9,T17,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T130,T131,T132
1	0	1	Covered	T9,T17,T4
1	1	0	Not Covered
1	1	1	Covered	T9,T7,T13

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T9,T17,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T9,T17,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T17,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	462905526	1381784	0	0
DepthKnown_A	463260986	462952016	0	0
RvalidKnown_A	463260986	462952016	0	0
WreadyKnown_A	463260986	462952016	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	463260986	1459991	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	462905526	1381784	0	0
T4	276	53	0	0
T5	218	0	0	0
T6	988360	0	0	0
T7	264	71	0	0
T8	0	65	0	0
T9	17564	11824	0	0
T10	0	2048	0	0
T11	0	1857	0	0
T13	0	1357	0	0
T17	4486	270	0	0
T18	0	744	0	0
T25	5718	0	0	0
T26	10240	0	0	0
T28	0	7432	0	0
T33	2286	0	0	0
T35	29466	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463260986	462952016	0	0
T1	6962	6852	0	0
T2	6336	6168	0	0
T3	4052	3872	0	0
T4	1602	1272	0	0
T5	2338	2014	0	0
T6	988360	988332	0	0
T9	17564	17430	0	0
T17	4486	4326	0	0
T25	5718	5566	0	0
T35	29466	28810	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463260986	462952016	0	0
T1	6962	6852	0	0
T2	6336	6168	0	0
T3	4052	3872	0	0
T4	1602	1272	0	0
T5	2338	2014	0	0
T6	988360	988332	0	0
T9	17564	17430	0	0
T17	4486	4326	0	0
T25	5718	5566	0	0
T35	29466	28810	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	463260986	462952016	0	0
T1	6962	6852	0	0
T2	6336	6168	0	0
T3	4052	3872	0	0
T4	1602	1272	0	0
T5	2338	2014	0	0
T6	988360	988332	0	0
T9	17564	17430	0	0
T17	4486	4326	0	0
T25	5718	5566	0	0
T35	29466	28810	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	463260986	1459991	0	0
T4	1602	620	0	0
T5	2338	276	0	0
T6	988360	0	0	0
T7	2566	1175	0	0
T8	0	634	0	0
T9	17564	11824	0	0
T10	0	2048	0	0
T11	0	1857	0	0
T13	0	1357	0	0
T17	4486	270	0	0
T25	5718	0	0	0
T26	10240	0	0	0
T27	0	220	0	0
T33	2286	0	0	0
T35	29466	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T17,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T17,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T127,T128,T133
1	1	0	Not Covered
1	1	1	Covered	T9,T17,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T9,T17,T4
1	1	0	Not Covered
1	1	1	Covered	T9,T7,T13

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T9,T17,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T9,T17,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T17,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	231452763	695748	0	0
DepthKnown_A	231630493	231476008	0	0
RvalidKnown_A	231630493	231476008	0	0
WreadyKnown_A	231630493	231476008	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	231630493	735195	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231452763	695748	0	0
T4	138	30	0	0
T5	109	0	0	0
T6	494180	0	0	0
T7	132	48	0	0
T8	0	38	0	0
T9	8782	5934	0	0
T10	0	1060	0	0
T11	0	964	0	0
T13	0	710	0	0
T17	2243	174	0	0
T18	0	369	0	0
T25	2859	0	0	0
T26	5120	0	0	0
T28	0	3759	0	0
T33	1143	0	0	0
T35	14733	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231630493	231476008	0	0
T1	3481	3426	0	0
T2	3168	3084	0	0
T3	2026	1936	0	0
T4	801	636	0	0
T5	1169	1007	0	0
T6	494180	494166	0	0
T9	8782	8715	0	0
T17	2243	2163	0	0
T25	2859	2783	0	0
T35	14733	14405	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231630493	231476008	0	0
T1	3481	3426	0	0
T2	3168	3084	0	0
T3	2026	1936	0	0
T4	801	636	0	0
T5	1169	1007	0	0
T6	494180	494166	0	0
T9	8782	8715	0	0
T17	2243	2163	0	0
T25	2859	2783	0	0
T35	14733	14405	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231630493	231476008	0	0
T1	3481	3426	0	0
T2	3168	3084	0	0
T3	2026	1936	0	0
T4	801	636	0	0
T5	1169	1007	0	0
T6	494180	494166	0	0
T9	8782	8715	0	0
T17	2243	2163	0	0
T25	2859	2783	0	0
T35	14733	14405	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	231630493	735195	0	0
T4	801	319	0	0
T5	1169	137	0	0
T6	494180	0	0	0
T7	1283	604	0	0
T8	0	327	0	0
T9	8782	5934	0	0
T10	0	1060	0	0
T11	0	964	0	0
T13	0	710	0	0
T17	2243	174	0	0
T25	2859	0	0	0
T26	5120	0	0	0
T27	0	109	0	0
T33	1143	0	0	0
T35	14733	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T42,T85,T134
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T9,T17,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T129
1	1	0	Not Covered
1	1	1	Covered	T9,T17,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T130,T131,T132
1	0	1	Covered	T9,T17,T4
1	1	0	Not Covered
1	1	1	Covered	T9,T7,T13

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T9,T17,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T9,T17,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T9,T17,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	231452763	686036	0	0
DepthKnown_A	231630493	231476008	0	0
RvalidKnown_A	231630493	231476008	0	0
WreadyKnown_A	231630493	231476008	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	231630493	724796	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231452763	686036	0	0
T4	138	23	0	0
T5	109	0	0	0
T6	494180	0	0	0
T7	132	23	0	0
T8	0	27	0	0
T9	8782	5890	0	0
T10	0	988	0	0
T11	0	893	0	0
T13	0	647	0	0
T17	2243	96	0	0
T18	0	375	0	0
T25	2859	0	0	0
T26	5120	0	0	0
T28	0	3673	0	0
T33	1143	0	0	0
T35	14733	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231630493	231476008	0	0
T1	3481	3426	0	0
T2	3168	3084	0	0
T3	2026	1936	0	0
T4	801	636	0	0
T5	1169	1007	0	0
T6	494180	494166	0	0
T9	8782	8715	0	0
T17	2243	2163	0	0
T25	2859	2783	0	0
T35	14733	14405	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231630493	231476008	0	0
T1	3481	3426	0	0
T2	3168	3084	0	0
T3	2026	1936	0	0
T4	801	636	0	0
T5	1169	1007	0	0
T6	494180	494166	0	0
T9	8782	8715	0	0
T17	2243	2163	0	0
T25	2859	2783	0	0
T35	14733	14405	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	231630493	231476008	0	0
T1	3481	3426	0	0
T2	3168	3084	0	0
T3	2026	1936	0	0
T4	801	636	0	0
T5	1169	1007	0	0
T6	494180	494166	0	0
T9	8782	8715	0	0
T17	2243	2163	0	0
T25	2859	2783	0	0
T35	14733	14405	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	231630493	724796	0	0
T4	801	301	0	0
T5	1169	139	0	0
T6	494180	0	0	0
T7	1283	571	0	0
T8	0	307	0	0
T9	8782	5890	0	0
T10	0	988	0	0
T11	0	893	0	0
T13	0	647	0	0
T17	2243	96	0	0
T25	2859	0	0	0
T26	5120	0	0	0
T27	0	111	0	0
T33	1143	0	0	0
T35	14733	0	0	0