Module Definition
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Module : prim_count
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.30 70.30

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_edn_core.u_prim_count_max_reqs_cntr 70.30 70.30



Module Instance : tb.dut.u_edn_core.u_prim_count_max_reqs_cntr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.30 70.30


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.30 70.30


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.41 100.00 89.63 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : prim_count
TotalCoveredPercent
Totals 8 7 87.50
Total Bits 202 142 70.30
Total Bits 0->1 101 72 71.29
Total Bits 1->0 101 70 69.31

Ports 8 7 87.50
Port Bits 202 142 70.30
Port Bits 0->1 101 72 71.29
Port Bits 1->0 101 70 69.31

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_cnt_i[0] Yes Yes *T4,*T7,*T8 Yes T9,T4,T7 INPUT
set_cnt_i[2:1] No No Yes T10,T11,T12 INPUT
set_cnt_i[31:3] No No No INPUT
incr_en_i Unreachable Unreachable Unreachable INPUT
decr_en_i Yes Yes T9,T7,T13 Yes T9,T7,T13 INPUT
step_i[31:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[31:0] Yes Yes T9,T4,T7 Yes T9,T4,T7 OUTPUT
cnt_after_commit_o[31:0] Yes Yes T9,T4,T7 Yes T9,T4,T7 OUTPUT
err_o Yes Yes T14,T15,T16 Yes T14,T15,T16 OUTPUT

*Tests covering at least one bit in the range
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%