Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	635189	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5075383

1

T1

21

T2

8

T3

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1515728	1			T1	35		T2	25		T3	17
values[0x0]	1938998	1			T1	10		T2	3		T3	4
values[0x1]	2255846	1			T1	7		T2	6		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	316451	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5394121

1

T1

33

T2

10

T3

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23966	1			T20	1		T22	5		T56	1
valid_sources[0x01]	21673	1			T2	1		T33	1		T56	1
valid_sources[0x02]	21536	1			T5	2		T8	4		T20	2
valid_sources[0x03]	23152	1			T3	1		T32	1		T33	1
valid_sources[0x04]	18448	1			T5	2		T32	1		T20	2
valid_sources[0x05]	22353	1			T30	6		T35	3		T41	6
valid_sources[0x06]	21830	1			T5	4		T8	1		T44	1
valid_sources[0x07]	22198	1			T1	1		T32	1		T29	1
valid_sources[0x08]	22381	1			T8	4		T20	1		T33	2
valid_sources[0x09]	22490	1			T1	1		T5	1		T22	1
valid_sources[0x0a]	24493	1			T5	1		T8	3		T33	1
valid_sources[0x0b]	20517	1			T2	1		T8	1		T20	1
valid_sources[0x0c]	24097	1			T5	2		T8	1		T32	1
valid_sources[0x0d]	22888	1			T5	1		T8	1		T32	1
valid_sources[0x0e]	25171	1			T22	6		T33	1		T30	3
valid_sources[0x0f]	24044	1			T5	1		T20	1		T22	2
valid_sources[0x10]	23585	1			T1	1		T22	6		T33	2
valid_sources[0x11]	22168	1			T5	1		T44	1		T33	1
valid_sources[0x12]	22963	1			T3	3		T5	3		T20	1
valid_sources[0x13]	24857	1			T8	1		T29	2		T30	1
valid_sources[0x14]	24489	1			T8	3		T29	4		T30	3
valid_sources[0x15]	24443	1			T12	1		T30	3		T144	2
valid_sources[0x16]	24347	1			T33	1		T56	1		T265	1
valid_sources[0x17]	22661	1			T5	4		T8	1		T20	1
valid_sources[0x18]	23234	1			T21	3		T30	1		T14	1
valid_sources[0x19]	21739	1			T8	1		T32	1		T29	1
valid_sources[0x1a]	23454	1			T30	1		T56	1		T31	1
valid_sources[0x1b]	21632	1			T1	1		T5	1		T20	1
valid_sources[0x1c]	21954	1			T30	3		T15	1		T134	2
valid_sources[0x1d]	20399	1			T1	1		T5	2		T22	2
valid_sources[0x1e]	21959	1			T5	3		T8	1		T29	1
valid_sources[0x1f]	21875	1			T3	1		T5	3		T33	1
valid_sources[0x20]	22360	1			T1	1		T5	2		T22	2
valid_sources[0x21]	21551	1			T32	1		T33	1		T29	1
valid_sources[0x22]	21486	1			T2	4		T5	1		T20	2
valid_sources[0x23]	23044	1			T56	1		T35	4		T16	1
valid_sources[0x24]	21707	1			T8	2		T29	3		T30	2
valid_sources[0x25]	22023	1			T22	4		T144	3		T35	2
valid_sources[0x26]	23741	1			T32	1		T22	1		T30	2
valid_sources[0x27]	23506	1			T1	1		T5	1		T12	2
valid_sources[0x28]	23132	1			T27	141		T33	1		T29	1
valid_sources[0x29]	22566	1			T3	2		T5	1		T32	3
valid_sources[0x2a]	24157	1			T1	1		T22	1		T56	1
valid_sources[0x2b]	23552	1			T5	2		T30	1		T15	1
valid_sources[0x2c]	23041	1			T8	1		T29	2		T30	1
valid_sources[0x2d]	21666	1			T5	3		T20	1		T30	1
valid_sources[0x2e]	22261	1			T2	1		T32	1		T22	1
valid_sources[0x2f]	22649	1			T5	3		T8	1		T29	1
valid_sources[0x30]	22427	1			T2	1		T5	2		T32	1
valid_sources[0x31]	22386	1			T5	1		T8	1		T44	1
valid_sources[0x32]	22466	1			T8	1		T32	1		T22	1
valid_sources[0x33]	22504	1			T5	2		T8	3		T20	1
valid_sources[0x34]	21882	1			T20	1		T29	1		T40	1
valid_sources[0x35]	21746	1			T2	4		T30	1		T35	1
valid_sources[0x36]	23899	1			T5	2		T22	4		T29	2
valid_sources[0x37]	23718	1			T5	1		T21	5		T22	1
valid_sources[0x38]	22385	1			T1	2		T5	2		T8	2
valid_sources[0x39]	20215	1			T5	1		T20	1		T12	1
valid_sources[0x3a]	21999	1			T32	2		T44	1		T33	1
valid_sources[0x3b]	22614	1			T8	2		T32	1		T22	1
valid_sources[0x3c]	22898	1			T3	1		T12	1		T30	1
valid_sources[0x3d]	22290	1			T2	1		T20	2		T22	3
valid_sources[0x3e]	20592	1			T1	1		T22	3		T12	2
valid_sources[0x3f]	20473	1			T20	1		T29	1		T30	3
valid_sources[0x40]	24158	1			T1	1		T5	1		T8	1
valid_sources[0x41]	21974	1			T8	1		T20	1		T134	1
valid_sources[0x42]	22193	1			T32	1		T30	2		T56	1
valid_sources[0x43]	22399	1			T5	4		T31	1		T35	1
valid_sources[0x44]	21507	1			T5	1		T8	2		T20	1
valid_sources[0x45]	21395	1			T5	1		T32	2		T44	1
valid_sources[0x46]	23279	1			T4	74		T5	2		T8	1
valid_sources[0x47]	22023	1			T5	4		T8	1		T22	3
valid_sources[0x48]	22353	1			T1	1		T5	2		T8	3
valid_sources[0x49]	21435	1			T1	2		T5	1		T8	2
valid_sources[0x4a]	21613	1			T32	4		T20	1		T22	1
valid_sources[0x4b]	22308	1			T8	1		T30	1		T265	3
valid_sources[0x4c]	21872	1			T29	4		T30	2		T15	1
valid_sources[0x4d]	21977	1			T8	1		T32	4		T33	1
valid_sources[0x4e]	20822	1			T3	4		T33	1		T30	1
valid_sources[0x4f]	22149	1			T1	1		T2	2		T32	1
valid_sources[0x50]	22318	1			T5	1		T32	1		T22	1
valid_sources[0x51]	22422	1			T5	1		T32	5		T33	2
valid_sources[0x52]	24580	1			T1	1		T2	4		T32	7
valid_sources[0x53]	22544	1			T1	1		T3	3		T5	3
valid_sources[0x54]	22363	1			T5	4		T22	6		T29	3
valid_sources[0x55]	21198	1			T5	1		T32	4		T30	2
valid_sources[0x56]	21616	1			T5	3		T33	2		T12	2
valid_sources[0x57]	21961	1			T3	1		T8	2		T32	2
valid_sources[0x58]	22646	1			T20	2		T12	1		T30	2
valid_sources[0x59]	23868	1			T5	3		T32	2		T22	1
valid_sources[0x5a]	20822	1			T1	2		T5	1		T32	1
valid_sources[0x5b]	22962	1			T5	3		T8	1		T32	1
valid_sources[0x5c]	22204	1			T1	1		T3	1		T5	1
valid_sources[0x5d]	22263	1			T5	2		T30	2		T35	1
valid_sources[0x5e]	22184	1			T5	2		T12	2		T56	1
valid_sources[0x5f]	23076	1			T5	2		T8	1		T22	1
valid_sources[0x60]	21775	1			T2	6		T8	2		T22	1
valid_sources[0x61]	22115	1			T5	2		T32	3		T21	3
valid_sources[0x62]	23149	1			T5	4		T22	1		T33	2
valid_sources[0x63]	22377	1			T5	1		T44	1		T15	1
valid_sources[0x64]	22816	1			T5	3		T8	1		T15	1
valid_sources[0x65]	21059	1			T3	1		T5	1		T8	3
valid_sources[0x66]	22139	1			T2	1		T5	2		T30	2
valid_sources[0x67]	22583	1			T3	2		T5	1		T21	4
valid_sources[0x68]	20761	1			T32	1		T30	1		T56	1
valid_sources[0x69]	22269	1			T5	1		T8	1		T33	1
valid_sources[0x6a]	21216	1			T1	2		T2	1		T3	1
valid_sources[0x6b]	23423	1			T21	5		T30	3		T134	1
valid_sources[0x6c]	20194	1			T5	2		T20	1		T30	1
valid_sources[0x6d]	22146	1			T5	1		T33	1		T30	3
valid_sources[0x6e]	24179	1			T8	1		T20	1		T30	1
valid_sources[0x6f]	22095	1			T5	1		T32	1		T29	2
valid_sources[0x70]	20341	1			T32	1		T20	1		T33	1
valid_sources[0x71]	21010	1			T5	7		T32	3		T44	1
valid_sources[0x72]	22459	1			T1	3		T5	1		T32	2
valid_sources[0x73]	22243	1			T5	1		T15	1		T35	5
valid_sources[0x74]	22206	1			T1	1		T5	5		T32	2
valid_sources[0x75]	21286	1			T8	3		T30	5		T35	4
valid_sources[0x76]	24359	1			T5	2		T29	2		T12	1
valid_sources[0x77]	22003	1			T33	2		T30	1		T265	1
valid_sources[0x78]	21143	1			T5	1		T8	1		T32	1
valid_sources[0x79]	22074	1			T5	1		T20	1		T33	1
valid_sources[0x7a]	21433	1			T5	1		T26	66		T8	1
valid_sources[0x7b]	22271	1			T5	1		T32	1		T30	1
valid_sources[0x7c]	22555	1			T1	1		T5	1		T44	1
valid_sources[0x7d]	24241	1			T1	1		T2	1		T5	1
valid_sources[0x7e]	21507	1			T5	1		T8	1		T32	1
valid_sources[0x7f]	23478	1			T5	1		T8	1		T30	2
valid_sources[0x80]	22537	1			T5	1		T29	1		T30	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1279254

1

T1

7

T2

5

T3

1

values[0x0]

all_enables

biggest_size

1898018

1

T1

9

T2

1

T3

2

values[0x1]

all_enables

biggest_size

1898111

1

T1

5

T2

2

T3

1