Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
67.19	67.19	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	67.19	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
67.19	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	21	31	59.62

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	21	31	59.62	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2731	1			T1	3		T21	2		T33	2
non_zero_bins[1]	1885	1			T27	1		T8	2		T32	2
zero	8653	1			T1	1		T2	3		T3	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	507	1			T1	1		T35	1		T142	1
uni	3675	1			T1	1		T2	1		T26	1
gen	4030	1			T1	1		T2	1		T3	1
res	878	1			T8	2		T32	1		T21	1
ins	4179	1			T1	1		T2	1		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8993

1

T1

1

T2

2

T3

2

mubi_true

4276

1

T1

3

T2

1

T26

1

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

31

1

T16

1

T17

1

T39

1

pass

13238

1

T1

4

T2

3

T3

2

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	21	31	59.62	21
Automatically Generated Cross Bins	52	21	31	59.62	21
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	4

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	129	1			T41	1		T24	1		T25	1
upd	non_zero_bins[0]	pass	mubi_true	124	1			T1	1		T34	1		T41	1
upd	non_zero_bins[1]	pass	mubi_false	82	1			T35	1		T142	1		T260	1
upd	non_zero_bins[1]	pass	mubi_true	85	1			T261	1		T23	2		T25	2
upd	zero	pass	mubi_false	46	1			T43	1		T25	1		T262	1
upd	zero	pass	mubi_true	41	1			T191	1		T192	3		T193	2
uni	zero	fail	mubi_false	5	1			T16	1		T263	1		T264	1
uni	zero	pass	mubi_false	2661	1			T1	1		T32	1		T20	1
uni	zero	pass	mubi_true	1009	1			T2	1		T26	1		T33	1
gen	non_zero_bins[0]	pass	mubi_false	487	1			T21	1		T12	1		T62	1
gen	non_zero_bins[0]	pass	mubi_true	500	1			T1	1		T34	1		T41	2
gen	non_zero_bins[1]	pass	mubi_false	339	1			T189	1		T141	1		T190	4
gen	non_zero_bins[1]	pass	mubi_true	378	1			T32	1		T33	1		T265	1
gen	zero	fail	mubi_false	21	1			T17	1		T147	1		T101	1
gen	zero	pass	mubi_false	1877	1			T2	1		T3	1		T4	1
gen	zero	pass	mubi_true	428	1			T21	1		T12	3		T56	1
res	non_zero_bins[0]	pass	mubi_false	220	1			T41	1		T85	3		T78	5
res	non_zero_bins[0]	pass	mubi_true	201	1			T21	1		T12	2		T85	1
res	non_zero_bins[1]	pass	mubi_false	117	1			T32	1		T62	1		T190	2
res	non_zero_bins[1]	pass	mubi_true	146	1			T122	2		T41	1		T140	1
res	zero	fail	mubi_false	3	1			T266	1		T180	1		T181	1
res	zero	pass	mubi_false	104	1			T15	1		T37	2		T23	1
res	zero	pass	mubi_true	87	1			T8	2		T64	4		T41	2
ins	non_zero_bins[0]	pass	mubi_false	549	1			T29	1		T56	1		T37	2
ins	non_zero_bins[0]	pass	mubi_true	521	1			T1	1		T33	2		T265	1
ins	non_zero_bins[1]	pass	mubi_false	391	1			T27	1		T22	1		T56	1
ins	non_zero_bins[1]	pass	mubi_true	347	1			T8	2		T144	1		T31	1
ins	zero	fail	mubi_false	1	1			T106	1		-	-		-	-
ins	zero	fail	mubi_true	1	1			T39	1		-	-		-	-
ins	zero	pass	mubi_false	1961	1			T2	1		T3	1		T4	1
ins	zero	pass	mubi_true	408	1			T32	1		T21	1		T28	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded