Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	210328860	8961324	0	0
boot_gen_cmd_rd_A	210328860	64184	0	0
boot_ins_cmd_rd_A	210328860	72189	0	0
ctrl_rd_A	210328860	63505	0	0
err_code_test_rd_A	210328860	72368	0	0
intr_enable_rd_A	210328860	71437	0	0
max_num_reqs_between_reseeds_rd_A	210328860	63617	0	0
regwen_rd_A	210328860	72482	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210328860	8961324	0	0
T9	2638	0	0	0
T23	381685	149958	0	0
T24	402250	163156	0	0
T25	0	94988	0	0
T48	2312	0	0	0
T150	1014	0	0	0
T152	1123	0	0	0
T191	0	207277	0	0
T192	0	233157	0	0
T193	0	193630	0	0
T194	0	182406	0	0
T195	0	234600	0	0
T196	0	118831	0	0
T197	0	316317	0	0
T198	3731	0	0	0
T199	2847	0	0	0
T200	5169	0	0	0
T201	1779	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210328860	64184	0	0
T202	278794	1441	0	0
T203	493583	5012	0	0
T204	0	2176	0	0
T205	0	5414	0	0
T206	0	5955	0	0
T207	0	1583	0	0
T208	0	3160	0	0
T209	0	4442	0	0
T210	0	5279	0	0
T211	0	2475	0	0
T212	888	0	0	0
T213	14591	0	0	0
T214	6022	0	0	0
T215	3342	0	0	0
T216	904	0	0	0
T217	1949	0	0	0
T218	4500	0	0	0
T219	1358	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210328860	72189	0	0
T202	278794	1802	0	0
T203	493583	5413	0	0
T204	0	2494	0	0
T205	0	5856	0	0
T206	0	6543	0	0
T207	0	1493	0	0
T208	0	3529	0	0
T209	0	4933	0	0
T210	0	6214	0	0
T211	0	2832	0	0
T212	888	0	0	0
T213	14591	0	0	0
T214	6022	0	0	0
T215	3342	0	0	0
T216	904	0	0	0
T217	1949	0	0	0
T218	4500	0	0	0
T219	1358	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210328860	63505	0	0
T23	381685	0	0	0
T24	402250	0	0	0
T43	15806	5	0	0
T48	2312	0	0	0
T150	1014	0	0	0
T152	1123	0	0	0
T198	3731	0	0	0
T199	2847	0	0	0
T200	5169	0	0	0
T201	1779	0	0	0
T202	0	1566	0	0
T203	0	4922	0	0
T204	0	2412	0	0
T205	0	5327	0	0
T206	0	5371	0	0
T220	0	2	0	0
T221	0	4	0	0
T222	0	2	0	0
T223	0	8	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210328860	72368	0	0
T202	278794	1962	0	0
T203	493583	5481	0	0
T204	0	2425	0	0
T205	0	6021	0	0
T206	0	6195	0	0
T207	0	1874	0	0
T208	0	3396	0	0
T209	0	4981	0	0
T210	0	5943	0	0
T211	0	2771	0	0
T212	888	0	0	0
T213	14591	0	0	0
T214	6022	0	0	0
T215	3342	0	0	0
T216	904	0	0	0
T217	1949	0	0	0
T218	4500	0	0	0
T219	1358	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210328860	71437	0	0
T23	381685	0	0	0
T24	402250	0	0	0
T43	15806	43	0	0
T48	2312	0	0	0
T150	1014	0	0	0
T152	1123	0	0	0
T198	3731	0	0	0
T199	2847	0	0	0
T200	5169	0	0	0
T201	1779	0	0	0
T202	0	1627	0	0
T203	0	5282	0	0
T204	0	2440	0	0
T220	0	34	0	0
T224	0	53	0	0
T225	0	6	0	0
T226	0	14	0	0
T227	0	102	0	0
T228	0	143	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210328860	63617	0	0
T202	278794	1503	0	0
T203	493583	4852	0	0
T204	0	2268	0	0
T205	0	5270	0	0
T206	0	5238	0	0
T207	0	1594	0	0
T208	0	3097	0	0
T209	0	4093	0	0
T210	0	5156	0	0
T211	0	2554	0	0
T212	888	0	0	0
T213	14591	0	0	0
T214	6022	0	0	0
T215	3342	0	0	0
T216	904	0	0	0
T217	1949	0	0	0
T218	4500	0	0	0
T219	1358	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210328860	72482	0	0
T202	278794	1686	0	0
T203	493583	5881	0	0
T204	0	2320	0	0
T205	0	5867	0	0
T206	0	5984	0	0
T207	0	1755	0	0
T208	0	3657	0	0
T209	0	5082	0	0
T210	0	6283	0	0
T211	0	2915	0	0
T212	888	0	0	0
T213	14591	0	0	0
T214	6022	0	0	0
T215	3342	0	0	0
T216	904	0	0	0
T217	1949	0	0	0
T218	4500	0	0	0
T219	1358	0	0	0