Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	95.31	100.00	81.25			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	95.31	100.00	81.25			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T8,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T44,T124,T125
1	1	0	Not Covered
1	1	1	Covered	T4,T8,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T57,T59
1	0	1	Covered	T4,T8,T6
1	1	0	Not Covered
1	1	1	Covered	T4,T8,T6

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T8,T6
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T8,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	419165574	567080	0	0
DepthKnown_A	419510634	419247220	0	0
RvalidKnown_A	419510634	419247220	0	0
WreadyKnown_A	419510634	419247220	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	419510634	652254	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419165574	567080	0	0
T4	334	87	0	0
T5	36124	0	0	0
T6	240	51	0	0
T7	0	148	0	0
T8	4582	3496	0	0
T12	0	757	0	0
T15	0	612	0	0
T20	3484	0	0	0
T21	3294	0	0	0
T22	4148	0	0	0
T26	3124	0	0	0
T27	7642	0	0	0
T32	5086	0	0	0
T37	0	2522	0	0
T54	0	363	0	0
T64	0	2988	0	0
T122	0	1893	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419510634	419247220	0	0
T1	3982	3850	0	0
T2	2310	2208	0	0
T3	2122	1854	0	0
T4	1740	1416	0	0
T5	36124	21258	0	0
T6	1548	1304	0	0
T8	4582	4410	0	0
T26	3124	2936	0	0
T27	7642	7480	0	0
T32	5086	4962	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419510634	419247220	0	0
T1	3982	3850	0	0
T2	2310	2208	0	0
T3	2122	1854	0	0
T4	1740	1416	0	0
T5	36124	21258	0	0
T6	1548	1304	0	0
T8	4582	4410	0	0
T26	3124	2936	0	0
T27	7642	7480	0	0
T32	5086	4962	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	419510634	419247220	0	0
T1	3982	3850	0	0
T2	2310	2208	0	0
T3	2122	1854	0	0
T4	1740	1416	0	0
T5	36124	21258	0	0
T6	1548	1304	0	0
T8	4582	4410	0	0
T26	3124	2936	0	0
T27	7642	7480	0	0
T32	5086	4962	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	419510634	652254	0	0
T4	1740	781	0	0
T5	36124	0	0	0
T6	1548	654	0	0
T7	0	1211	0	0
T8	4582	3496	0	0
T12	0	757	0	0
T13	0	249	0	0
T15	0	612	0	0
T20	3484	0	0	0
T21	3294	0	0	0
T22	4148	0	0	0
T26	3124	0	0	0
T27	7642	0	0	0
T32	5086	0	0	0
T37	0	2522	0	0
T44	0	14	0	0
T64	0	2988	0	0
T122	0	934	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T44,T7,T64
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T8,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T44
1	1	0	Not Covered
1	1	1	Covered	T4,T8,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T57,T126
1	0	1	Covered	T4,T8,T6
1	1	0	Not Covered
1	1	1	Covered	T4,T8,T12

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T8,T6
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T8,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	209582787	278989	0	0
DepthKnown_A	209755317	209623610	0	0
RvalidKnown_A	209755317	209623610	0	0
WreadyKnown_A	209755317	209623610	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	209755317	321253	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209582787	278989	0	0
T4	167	37	0	0
T5	18062	0	0	0
T6	120	17	0	0
T7	0	70	0	0
T8	2291	1685	0	0
T12	0	338	0	0
T15	0	303	0	0
T20	1742	0	0	0
T21	1647	0	0	0
T22	2074	0	0	0
T26	1562	0	0	0
T27	3821	0	0	0
T32	2543	0	0	0
T37	0	1166	0	0
T54	0	127	0	0
T64	0	1432	0	0
T122	0	959	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209755317	209623610	0	0
T1	1991	1925	0	0
T2	1155	1104	0	0
T3	1061	927	0	0
T4	870	708	0	0
T5	18062	10629	0	0
T6	774	652	0	0
T8	2291	2205	0	0
T26	1562	1468	0	0
T27	3821	3740	0	0
T32	2543	2481	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209755317	209623610	0	0
T1	1991	1925	0	0
T2	1155	1104	0	0
T3	1061	927	0	0
T4	870	708	0	0
T5	18062	10629	0	0
T6	774	652	0	0
T8	2291	2205	0	0
T26	1562	1468	0	0
T27	3821	3740	0	0
T32	2543	2481	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209755317	209623610	0	0
T1	1991	1925	0	0
T2	1155	1104	0	0
T3	1061	927	0	0
T4	870	708	0	0
T5	18062	10629	0	0
T6	774	652	0	0
T8	2291	2205	0	0
T26	1562	1468	0	0
T27	3821	3740	0	0
T32	2543	2481	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	209755317	321253	0	0
T4	870	376	0	0
T5	18062	0	0	0
T6	774	309	0	0
T7	0	588	0	0
T8	2291	1685	0	0
T12	0	338	0	0
T13	0	126	0	0
T15	0	303	0	0
T20	1742	0	0	0
T21	1647	0	0	0
T22	2074	0	0	0
T26	1562	0	0	0
T27	3821	0	0	0
T32	2543	0	0	0
T37	0	1166	0	0
T44	0	14	0	0
T64	0	1432	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T4,T8,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T124,T125
1	1	0	Not Covered
1	1	1	Covered	T4,T8,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T59,T127,T128
1	0	1	Covered	T4,T8,T6
1	1	0	Not Covered
1	1	1	Covered	T4,T8,T6

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T4,T8,T6
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T8,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T4,T8,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	209582787	288091	0	0
DepthKnown_A	209755317	209623610	0	0
RvalidKnown_A	209755317	209623610	0	0
WreadyKnown_A	209755317	209623610	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	209755317	331001	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209582787	288091	0	0
T4	167	50	0	0
T5	18062	0	0	0
T6	120	34	0	0
T7	0	78	0	0
T8	2291	1811	0	0
T12	0	419	0	0
T15	0	309	0	0
T20	1742	0	0	0
T21	1647	0	0	0
T22	2074	0	0	0
T26	1562	0	0	0
T27	3821	0	0	0
T32	2543	0	0	0
T37	0	1356	0	0
T54	0	236	0	0
T64	0	1556	0	0
T122	0	934	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209755317	209623610	0	0
T1	1991	1925	0	0
T2	1155	1104	0	0
T3	1061	927	0	0
T4	870	708	0	0
T5	18062	10629	0	0
T6	774	652	0	0
T8	2291	2205	0	0
T26	1562	1468	0	0
T27	3821	3740	0	0
T32	2543	2481	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209755317	209623610	0	0
T1	1991	1925	0	0
T2	1155	1104	0	0
T3	1061	927	0	0
T4	870	708	0	0
T5	18062	10629	0	0
T6	774	652	0	0
T8	2291	2205	0	0
T26	1562	1468	0	0
T27	3821	3740	0	0
T32	2543	2481	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209755317	209623610	0	0
T1	1991	1925	0	0
T2	1155	1104	0	0
T3	1061	927	0	0
T4	870	708	0	0
T5	18062	10629	0	0
T6	774	652	0	0
T8	2291	2205	0	0
T26	1562	1468	0	0
T27	3821	3740	0	0
T32	2543	2481	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	209755317	331001	0	0
T4	870	405	0	0
T5	18062	0	0	0
T6	774	345	0	0
T7	0	623	0	0
T8	2291	1811	0	0
T12	0	419	0	0
T13	0	123	0	0
T15	0	309	0	0
T20	1742	0	0	0
T21	1647	0	0	0
T22	2074	0	0	0
T26	1562	0	0	0
T27	3821	0	0	0
T32	2543	0	0	0
T37	0	1356	0	0
T64	0	1556	0	0
T122	0	934	0	0