Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	131	1			T2	1		T27	1		T22	1
auto_req_mode	132	1			T7	1		T9	1		T19	1
sw_mode	3024	1			T44	1		T16	60		T17	49

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

296

1

T7

1

T9

1

T19

1

single

92

1

T2

1

T163

1

T22

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1484	1			T7	1		T27	1		T163	1
auto[2]	13	1			T28	1		T250	1		T251	1
auto[3]	230	1			T20	1		T180	56		T228	1
auto[4]	136	1			T16	60		T252	1		T253	1
auto[5]	129	1			T24	1		T168	1		T169	1
auto[6]	148	1			T18	76		T254	1		T255	1
auto[7]	1147	1			T2	1		T9	1		T19	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	83	1			T27	1		T22	1		T32	1
auto[1]	auto_req_mode	87	1			T7	1		T178	1		T179	1
auto[1]	sw_mode	1314	1			T163	1		T256	1		T257	1
auto[2]	boot_req_mode	5	1			T28	1		T251	1		T258	1
auto[2]	auto_req_mode	3	1			T250	1		T259	1		T260	1
auto[2]	sw_mode	5	1			T261	1		T262	1		T263	1
auto[3]	boot_req_mode	4	1			T228	1		T264	1		T265	1
auto[3]	auto_req_mode	3	1			T20	1		T266	1		T267	1
auto[3]	sw_mode	223	1			T180	56		T268	1		T181	56
auto[4]	boot_req_mode	5	1			T269	1		T270	1		T271	1
auto[4]	auto_req_mode	2	1			T272	1		T273	1		-	-
auto[4]	sw_mode	129	1			T16	60		T252	1		T253	1
auto[5]	boot_req_mode	3	1			T274	1		T275	1		T276	1
auto[5]	auto_req_mode	2	1			T169	1		T277	1		-	-
auto[5]	sw_mode	124	1			T24	1		T168	1		T278	1
auto[6]	boot_req_mode	1	1			T279	1		-	-		-	-
auto[6]	auto_req_mode	3	1			T280	1		T281	1		T282	1
auto[6]	sw_mode	144	1			T18	76		T254	1		T255	1
auto[7]	boot_req_mode	30	1			T2	1		T171	1		T34	1
auto[7]	auto_req_mode	32	1			T9	1		T19	1		T36	1
auto[7]	sw_mode	1085	1			T44	1		T17	49		T145	9