Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
65.62	65.62	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	65.62	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
65.62	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	22	30	57.69

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	22	30	57.69	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2577	1			T2	1		T7	4		T9	14
non_zero_bins[1]	1837	1			T2	2		T7	2		T9	2
zero	8694	1			T1	2		T2	5		T3	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	508	1			T27	1		T16	14		T17	9
uni	3701	1			T2	3		T7	1		T8	1
gen	3915	1			T1	1		T2	2		T3	1
res	822	1			T7	2		T9	2		T19	2
ins	4162	1			T1	1		T2	3		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8910

1

T1

2

T2

4

T3

2

mubi_true

4198

1

T2

4

T7

4

T8

5

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

38

1

T13

1

T39

1

T40

1

pass

13070

1

T1

2

T2

8

T3

2

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	22	30	57.69	22
Automatically Generated Cross Bins	52	22	30	57.69	22
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res , ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	12

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res , ins]	[zero]	[fail]	[mubi_true]	--	--	3

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	113	1			T27	1		T16	4		T18	1
upd	non_zero_bins[0]	pass	mubi_true	133	1			T16	3		T17	3		T18	2
upd	non_zero_bins[1]	pass	mubi_false	83	1			T16	2		T18	3		T147	1
upd	non_zero_bins[1]	pass	mubi_true	68	1			T16	4		T17	2		T163	1
upd	zero	pass	mubi_false	48	1			T18	1		T145	1		T147	1
upd	zero	pass	mubi_true	63	1			T16	1		T17	4		T18	2
uni	zero	fail	mubi_false	8	1			T121	1		T226	1		T167	1
uni	zero	pass	mubi_false	2712	1			T2	2		T7	1		T8	1
uni	zero	pass	mubi_true	981	1			T2	1		T16	15		T17	17
gen	non_zero_bins[0]	pass	mubi_false	455	1			T7	3		T16	7		T17	10
gen	non_zero_bins[0]	pass	mubi_true	472	1			T7	1		T9	13		T27	1
gen	non_zero_bins[1]	pass	mubi_false	329	1			T19	2		T16	4		T17	3
gen	non_zero_bins[1]	pass	mubi_true	310	1			T2	1		T44	1		T16	6
gen	zero	fail	mubi_false	19	1			T13	1		T39	1		T40	1
gen	zero	pass	mubi_false	1880	1			T1	1		T2	1		T3	1
gen	zero	pass	mubi_true	450	1			T8	3		T45	2		T16	4
res	non_zero_bins[0]	pass	mubi_false	163	1			T44	1		T16	4		T17	1
res	non_zero_bins[0]	pass	mubi_true	192	1			T19	2		T16	1		T17	1
res	non_zero_bins[1]	pass	mubi_false	141	1			T9	2		T16	2		T17	2
res	non_zero_bins[1]	pass	mubi_true	146	1			T7	2		T17	1		T18	4
res	zero	fail	mubi_false	9	1			T154	1		T151	1		T162	1
res	zero	pass	mubi_false	97	1			T16	1		T17	1		T18	2
res	zero	pass	mubi_true	74	1			T16	1		T17	1		T18	2
ins	non_zero_bins[0]	pass	mubi_false	517	1			T2	1		T16	16		T17	6
ins	non_zero_bins[0]	pass	mubi_true	532	1			T9	1		T27	1		T16	9
ins	non_zero_bins[1]	pass	mubi_false	387	1			T19	1		T44	1		T16	11
ins	non_zero_bins[1]	pass	mubi_true	373	1			T2	1		T16	6		T17	5
ins	zero	fail	mubi_false	2	1			T103	1		T104	1		-	-
ins	zero	pass	mubi_false	1947	1			T1	1		T3	1		T8	1
ins	zero	pass	mubi_true	404	1			T2	1		T7	1		T8	2

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded