Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	140	1			T2	1		T3	1		T24	1
auto_req_mode	135	1			T1	1		T9	1		T10	1
sw_mode	2706	1			T6	9		T16	1		T17	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

293

1

T1

1

T2

1

T3

1

single

98

1

T16

1

T17

1

T25

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1430	1			T1	1		T2	1		T6	9
auto[2]	139	1			T99	10		T130	1		T38	1
auto[3]	37	1			T150	5		T260	1		T261	1
auto[4]	144	1			T16	1		T17	1		T134	1
auto[5]	9	1			T137	1		T262	1		T263	1
auto[6]	184	1			T121	12		T112	1		T264	4
auto[7]	1038	1			T3	1		T10	1		T24	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	88	1			T2	1		T25	1		T20	1
auto[1]	auto_req_mode	78	1			T1	1		T9	1		T26	1
auto[1]	sw_mode	1264	1			T6	9		T100	1		T109	32
auto[2]	boot_req_mode	1	1			T265	1		-	-		-	-
auto[2]	auto_req_mode	4	1			T38	1		T266	1		T267	1
auto[2]	sw_mode	134	1			T99	10		T130	1		T268	10
auto[3]	boot_req_mode	2	1			T261	1		T269	1		-	-
auto[3]	auto_req_mode	4	1			T270	1		T271	1		T272	1
auto[3]	sw_mode	31	1			T150	5		T260	1		T273	1
auto[4]	boot_req_mode	5	1			T158	1		T274	1		T275	1
auto[4]	auto_req_mode	6	1			T276	1		T277	1		T278	1
auto[4]	sw_mode	133	1			T16	1		T17	1		T134	1
auto[5]	boot_req_mode	4	1			T137	1		T279	1		T280	1
auto[5]	auto_req_mode	2	1			T263	1		T281	1		-	-
auto[5]	sw_mode	3	1			T262	1		T282	1		T283	1
auto[6]	boot_req_mode	8	1			T112	1		T284	1		T285	1
auto[6]	auto_req_mode	3	1			T286	1		T287	1		T288	1
auto[6]	sw_mode	173	1			T121	12		T264	4		T289	66
auto[7]	boot_req_mode	32	1			T3	1		T24	1		T114	1
auto[7]	auto_req_mode	38	1			T10	1		T11	1		T143	1
auto[7]	sw_mode	968	1			T115	1		T110	60		T122	14