Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	661129	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5473431

1

T1

95

T2

5

T3

30

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1610074	1			T1	52		T2	1		T3	302
values[0x0]	2091204	1			T1	46		T2	5		T3	16
values[0x1]	2433282	1			T1	47		T3	15		T4	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	321787	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5812773

1

T1

109

T2

5

T3

119

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	25640	1			T6	5		T99	7		T109	138
valid_sources[0x01]	25180	1			T6	5		T24	2		T100	1
valid_sources[0x02]	25509	1			T6	2		T99	4		T24	1
valid_sources[0x03]	24031	1			T1	1		T6	4		T10	1
valid_sources[0x04]	24309	1			T6	1		T10	1		T99	3
valid_sources[0x05]	25047	1			T9	1		T10	4		T24	5
valid_sources[0x06]	24961	1			T17	1		T10	4		T99	2
valid_sources[0x07]	23732	1			T6	1		T99	1		T106	5
valid_sources[0x08]	23359	1			T1	1		T5	2		T6	2
valid_sources[0x09]	24098	1			T1	1		T6	4		T10	4
valid_sources[0x0a]	23785	1			T1	1		T6	1		T10	2
valid_sources[0x0b]	24689	1			T6	2		T99	1		T25	2
valid_sources[0x0c]	24103	1			T6	4		T17	1		T10	2
valid_sources[0x0d]	25608	1			T6	3		T17	1		T10	1
valid_sources[0x0e]	22979	1			T1	4		T4	4		T6	10
valid_sources[0x0f]	23338	1			T4	1		T6	2		T19	1
valid_sources[0x10]	24341	1			T17	1		T19	1		T10	1
valid_sources[0x11]	24409	1			T5	1		T6	4		T130	3
valid_sources[0x12]	23888	1			T6	10		T16	32		T10	1
valid_sources[0x13]	23504	1			T1	2		T6	3		T10	1
valid_sources[0x14]	24344	1			T99	7		T109	146		T110	707
valid_sources[0x15]	23908	1			T6	4		T17	1		T99	10
valid_sources[0x16]	25467	1			T1	4		T6	1		T17	2
valid_sources[0x17]	23982	1			T1	1		T4	1		T6	1
valid_sources[0x18]	23059	1			T17	1		T10	1		T99	12
valid_sources[0x19]	26125	1			T4	1		T6	2		T17	1
valid_sources[0x1a]	23400	1			T6	2		T10	3		T99	2
valid_sources[0x1b]	24791	1			T5	3		T6	3		T17	1
valid_sources[0x1c]	23223	1			T6	2		T19	1		T10	1
valid_sources[0x1d]	23240	1			T1	3		T4	1		T6	3
valid_sources[0x1e]	23057	1			T6	4		T10	3		T99	4
valid_sources[0x1f]	25179	1			T1	4		T17	2		T10	2
valid_sources[0x20]	24688	1			T1	1		T17	1		T99	3
valid_sources[0x21]	23343	1			T25	1		T109	142		T110	843
valid_sources[0x22]	22076	1			T17	1		T99	13		T24	8
valid_sources[0x23]	24177	1			T17	1		T109	165		T110	726
valid_sources[0x24]	23506	1			T6	3		T9	1		T99	6
valid_sources[0x25]	24011	1			T6	4		T106	1		T25	1
valid_sources[0x26]	24178	1			T99	8		T24	1		T106	3
valid_sources[0x27]	23284	1			T6	2		T99	1		T130	2
valid_sources[0x28]	24156	1			T1	1		T6	3		T17	2
valid_sources[0x29]	23934	1			T6	4		T99	1		T106	2
valid_sources[0x2a]	25809	1			T6	1		T17	2		T10	4
valid_sources[0x2b]	22592	1			T6	5		T10	1		T25	1
valid_sources[0x2c]	24686	1			T6	2		T16	2		T9	1
valid_sources[0x2d]	24180	1			T6	4		T17	1		T99	2
valid_sources[0x2e]	22630	1			T10	7		T99	9		T24	2
valid_sources[0x2f]	23846	1			T6	3		T19	2		T10	1
valid_sources[0x30]	25285	1			T6	3		T17	1		T99	2
valid_sources[0x31]	23072	1			T6	6		T17	1		T10	1
valid_sources[0x32]	24301	1			T6	2		T17	1		T99	2
valid_sources[0x33]	22780	1			T1	2		T19	1		T100	1
valid_sources[0x34]	24259	1			T1	3		T6	1		T17	1
valid_sources[0x35]	23604	1			T1	3		T6	5		T130	1
valid_sources[0x36]	22411	1			T6	2		T10	2		T99	3
valid_sources[0x37]	23889	1			T1	11		T6	3		T9	1
valid_sources[0x38]	24811	1			T1	2		T6	3		T99	1
valid_sources[0x39]	25346	1			T6	5		T9	3		T10	2
valid_sources[0x3a]	23706	1			T1	1		T6	2		T17	1
valid_sources[0x3b]	21731	1			T6	6		T17	3		T10	1
valid_sources[0x3c]	22511	1			T6	5		T17	1		T10	5
valid_sources[0x3d]	22015	1			T1	1		T6	9		T17	2
valid_sources[0x3e]	25248	1			T5	2		T19	2		T24	4
valid_sources[0x3f]	23447	1			T5	5		T6	1		T10	1
valid_sources[0x40]	23845	1			T6	4		T17	1		T99	2
valid_sources[0x41]	24212	1			T4	2		T6	4		T9	1
valid_sources[0x42]	23156	1			T6	1		T17	1		T9	4
valid_sources[0x43]	24625	1			T17	1		T10	4		T99	8
valid_sources[0x44]	24362	1			T1	2		T6	7		T17	2
valid_sources[0x45]	23317	1			T6	3		T99	6		T25	1
valid_sources[0x46]	23622	1			T5	1		T6	3		T10	1
valid_sources[0x47]	23863	1			T1	1		T6	6		T16	6
valid_sources[0x48]	23724	1			T6	7		T17	1		T99	2
valid_sources[0x49]	25111	1			T6	4		T17	1		T9	3
valid_sources[0x4a]	24186	1			T1	2		T6	2		T17	2
valid_sources[0x4b]	22819	1			T6	3		T9	1		T99	3
valid_sources[0x4c]	24502	1			T6	5		T9	1		T99	1
valid_sources[0x4d]	22713	1			T6	2		T17	1		T99	3
valid_sources[0x4e]	23546	1			T6	5		T9	2		T99	6
valid_sources[0x4f]	23483	1			T1	2		T5	1		T6	1
valid_sources[0x50]	24167	1			T1	1		T5	2		T6	2
valid_sources[0x51]	23711	1			T6	3		T99	5		T109	138
valid_sources[0x52]	22208	1			T5	1		T6	3		T10	3
valid_sources[0x53]	22406	1			T6	2		T17	2		T109	112
valid_sources[0x54]	24178	1			T1	3		T6	4		T10	2
valid_sources[0x55]	24332	1			T6	2		T16	21		T17	1
valid_sources[0x56]	23351	1			T6	3		T17	3		T99	2
valid_sources[0x57]	22559	1			T6	4		T17	3		T10	1
valid_sources[0x58]	24337	1			T6	5		T17	2		T25	1
valid_sources[0x59]	23443	1			T1	2		T5	2		T6	4
valid_sources[0x5a]	25490	1			T6	7		T9	1		T24	1
valid_sources[0x5b]	23017	1			T6	7		T10	3		T109	138
valid_sources[0x5c]	22883	1			T1	13		T6	3		T10	3
valid_sources[0x5d]	25235	1			T6	4		T10	4		T99	3
valid_sources[0x5e]	24197	1			T5	1		T6	3		T19	1
valid_sources[0x5f]	24917	1			T6	2		T9	1		T10	1
valid_sources[0x60]	22546	1			T6	2		T100	1		T109	136
valid_sources[0x61]	23457	1			T6	4		T10	1		T99	1
valid_sources[0x62]	24707	1			T6	2		T17	1		T19	1
valid_sources[0x63]	23889	1			T1	1		T6	4		T10	1
valid_sources[0x64]	23675	1			T5	6		T9	4		T10	1
valid_sources[0x65]	24278	1			T6	9		T10	2		T99	14
valid_sources[0x66]	25258	1			T6	1		T17	1		T10	1
valid_sources[0x67]	25838	1			T6	5		T17	1		T19	1
valid_sources[0x68]	24255	1			T1	2		T6	2		T25	1
valid_sources[0x69]	22776	1			T1	1		T6	2		T10	1
valid_sources[0x6a]	23404	1			T6	1		T10	2		T99	1
valid_sources[0x6b]	23802	1			T6	4		T109	156		T110	692
valid_sources[0x6c]	23937	1			T2	6		T6	2		T9	1
valid_sources[0x6d]	23098	1			T6	4		T99	4		T24	1
valid_sources[0x6e]	23842	1			T6	5		T17	1		T10	3
valid_sources[0x6f]	23671	1			T5	1		T6	1		T99	3
valid_sources[0x70]	24286	1			T6	9		T17	1		T10	4
valid_sources[0x71]	24873	1			T6	1		T17	1		T99	8
valid_sources[0x72]	23811	1			T6	2		T17	3		T10	2
valid_sources[0x73]	22988	1			T6	4		T16	16		T17	1
valid_sources[0x74]	24717	1			T1	5		T6	3		T99	3
valid_sources[0x75]	23186	1			T6	2		T99	4		T109	138
valid_sources[0x76]	24273	1			T6	7		T10	1		T99	3
valid_sources[0x77]	22826	1			T5	1		T6	8		T10	1
valid_sources[0x78]	23142	1			T5	2		T6	5		T10	2
valid_sources[0x79]	24489	1			T5	1		T6	8		T10	3
valid_sources[0x7a]	22480	1			T4	1		T5	2		T6	2
valid_sources[0x7b]	23884	1			T6	2		T99	2		T130	1
valid_sources[0x7c]	22060	1			T6	4		T17	1		T10	4
valid_sources[0x7d]	21931	1			T1	3		T6	3		T99	3
valid_sources[0x7e]	23320	1			T5	1		T6	1		T10	1
valid_sources[0x7f]	24731	1			T17	1		T99	9		T100	1
valid_sources[0x80]	23346	1			T6	3		T19	1		T10	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1378405

1

T1

5

T2

1

T3

4

values[0x0]

all_enables

biggest_size

2049000

1

T1

44

T2

4

T3

14

values[0x1]

all_enables

biggest_size

2046026

1

T1

46

T3

12

T4

2