Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
67.19	67.19	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	67.19	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
67.19	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	21	31	59.62

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	21	31	59.62	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2403	1			T3	1		T6	7		T16	1
non_zero_bins[1]	1646	1			T1	3		T3	2		T6	4
zero	8004	1			T2	4		T3	4		T4	6

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	453	1			T6	1		T99	2		T25	1
uni	3324	1			T3	2		T6	10		T99	10
gen	3701	1			T2	2		T3	2		T4	3
res	734	1			T1	1		T3	1		T6	2
ins	3841	1			T1	2		T2	2		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8165

1

T1

1

T2

2

T3

4

mubi_true

3888

1

T1

2

T2

2

T3

3

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

37

1

T21

1

T22

1

T23

1

pass

12016

1

T1

3

T2

4

T3

7

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	21	31	59.62	21
Automatically Generated Cross Bins	52	21	31	59.62	21
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	4

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	91	1			T99	1		T109	2		T110	1
upd	non_zero_bins[0]	pass	mubi_true	115	1			T109	2		T110	3		T150	1
upd	non_zero_bins[1]	pass	mubi_false	72	1			T110	2		T111	2		T181	1
upd	non_zero_bins[1]	pass	mubi_true	72	1			T99	1		T110	2		T137	1
upd	zero	pass	mubi_false	47	1			T6	1		T25	1		T110	2
upd	zero	pass	mubi_true	56	1			T110	2		T122	1		T111	2
uni	zero	fail	mubi_false	6	1			T90	1		T91	1		T92	1
uni	zero	pass	mubi_false	2390	1			T3	2		T6	6		T99	7
uni	zero	pass	mubi_true	928	1			T6	4		T99	3		T100	1
gen	non_zero_bins[0]	pass	mubi_false	490	1			T3	1		T6	2		T109	2
gen	non_zero_bins[0]	pass	mubi_true	414	1			T6	1		T99	1		T109	4
gen	non_zero_bins[1]	pass	mubi_false	278	1			T6	1		T99	2		T25	1
gen	non_zero_bins[1]	pass	mubi_true	324	1			T10	5		T109	4		T110	7
gen	zero	fail	mubi_false	23	1			T21	1		T22	1		T23	1
gen	zero	pass	mubi_false	1784	1			T2	2		T3	1		T4	1
gen	zero	pass	mubi_true	388	1			T4	2		T110	3		T112	1
res	non_zero_bins[0]	pass	mubi_false	189	1			T10	2		T130	1		T110	4
res	non_zero_bins[0]	pass	mubi_true	166	1			T6	1		T110	3		T112	1
res	non_zero_bins[1]	pass	mubi_false	107	1			T1	1		T9	3		T99	1
res	non_zero_bins[1]	pass	mubi_true	125	1			T3	1		T6	1		T110	2
res	zero	fail	mubi_false	1	1			T227	1		-	-		-	-
res	zero	pass	mubi_false	76	1			T110	2		T111	1		T53	1
res	zero	pass	mubi_true	70	1			T109	2		T111	1		T149	1
ins	non_zero_bins[0]	pass	mubi_false	456	1			T6	1		T9	1		T99	1
ins	non_zero_bins[0]	pass	mubi_true	482	1			T6	2		T16	1		T99	1
ins	non_zero_bins[1]	pass	mubi_false	325	1			T6	1		T10	1		T99	1
ins	non_zero_bins[1]	pass	mubi_true	343	1			T1	2		T3	1		T6	1
ins	zero	fail	mubi_false	4	1			T74	1		T228	1		T229	1
ins	zero	fail	mubi_true	3	1			T72	1		T154	1		T153	1
ins	zero	pass	mubi_false	1826	1			T4	2		T6	5		T18	1
ins	zero	pass	mubi_true	402	1			T2	2		T3	1		T4	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded