Module Definition
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Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.31 100.00 81.25 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.92 100.00 91.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.49 100.00 89.95 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.31 100.00 81.25 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.92 100.00 91.67 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.49 100.00 89.95 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Cond Coverage for Module : prim_fifo_sync
TotalCoveredPercent
Conditions161381.25
Logical161381.25
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T5,T18
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT18,T19,T144
110Not Covered
111CoveredT1,T4,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT104,T107,T108
101CoveredT1,T4,T5
110Not Covered
111CoveredT1,T9,T10

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3

Branch Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T4,T5


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 424428600 605625 0 0
DepthKnown_A 424810240 424500194 0 0
RvalidKnown_A 424810240 424500194 0 0
WreadyKnown_A 424810240 424500194 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 424810240 695495 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424428600 605625 0 0
T1 8068 6118 0 0
T2 2224 0 0 0
T3 3870 0 0 0
T4 326 0 0 0
T5 266 67 0 0
T6 26348 0 0 0
T7 0 206 0 0
T8 0 279 0 0
T9 0 2683 0 0
T10 0 1865 0 0
T11 0 3380 0 0
T16 5032 0 0 0
T17 7598 0 0 0
T18 586 0 0 0
T19 938 0 0 0
T26 0 2610 0 0
T38 0 9407 0 0
T39 0 1823 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424810240 424500194 0 0
T1 8068 7920 0 0
T2 2224 2060 0 0
T3 3870 3730 0 0
T4 1772 1474 0 0
T5 3126 2850 0 0
T6 26348 25622 0 0
T16 5032 4892 0 0
T17 7598 7466 0 0
T18 1294 1000 0 0
T19 4286 4010 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424810240 424500194 0 0
T1 8068 7920 0 0
T2 2224 2060 0 0
T3 3870 3730 0 0
T4 1772 1474 0 0
T5 3126 2850 0 0
T6 26348 25622 0 0
T16 5032 4892 0 0
T17 7598 7466 0 0
T18 1294 1000 0 0
T19 4286 4010 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 424810240 424500194 0 0
T1 8068 7920 0 0
T2 2224 2060 0 0
T3 3870 3730 0 0
T4 1772 1474 0 0
T5 3126 2850 0 0
T6 26348 25622 0 0
T16 5032 4892 0 0
T17 7598 7466 0 0
T18 1294 1000 0 0
T19 4286 4010 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 424810240 695495 0 0
T1 8068 6118 0 0
T2 2224 0 0 0
T3 3870 0 0 0
T4 1772 381 0 0
T5 3126 1128 0 0
T6 26348 0 0 0
T7 0 1126 0 0
T9 0 2683 0 0
T10 0 1865 0 0
T16 5032 0 0 0
T17 7598 0 0 0
T18 1294 22 0 0
T19 4286 20 0 0
T26 0 2610 0 0
T38 0 4702 0 0
T39 0 906 0 0
T59 0 128 0 0
T106 0 7 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
TotalCoveredPercent
Conditions161381.25
Logical161381.25
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT26,T8,T23
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT105,T145
110Not Covered
111CoveredT1,T4,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT104,T146
101CoveredT1,T4,T5
110Not Covered
111CoveredT1,T9,T10

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T4,T5


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 212214300 298491 0 0
DepthKnown_A 212405120 212250097 0 0
RvalidKnown_A 212405120 212250097 0 0
WreadyKnown_A 212405120 212250097 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 212405120 343295 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 212214300 298491 0 0
T1 4034 3043 0 0
T2 1112 0 0 0
T3 1935 0 0 0
T4 163 0 0 0
T5 133 31 0 0
T6 13174 0 0 0
T7 0 58 0 0
T8 0 139 0 0
T9 0 1320 0 0
T10 0 925 0 0
T11 0 1673 0 0
T16 2516 0 0 0
T17 3799 0 0 0
T18 293 0 0 0
T19 469 0 0 0
T26 0 1300 0 0
T38 0 4702 0 0
T39 0 906 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 212405120 212250097 0 0
T1 4034 3960 0 0
T2 1112 1030 0 0
T3 1935 1865 0 0
T4 886 737 0 0
T5 1563 1425 0 0
T6 13174 12811 0 0
T16 2516 2446 0 0
T17 3799 3733 0 0
T18 647 500 0 0
T19 2143 2005 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 212405120 212250097 0 0
T1 4034 3960 0 0
T2 1112 1030 0 0
T3 1935 1865 0 0
T4 886 737 0 0
T5 1563 1425 0 0
T6 13174 12811 0 0
T16 2516 2446 0 0
T17 3799 3733 0 0
T18 647 500 0 0
T19 2143 2005 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 212405120 212250097 0 0
T1 4034 3960 0 0
T2 1112 1030 0 0
T3 1935 1865 0 0
T4 886 737 0 0
T5 1563 1425 0 0
T6 13174 12811 0 0
T16 2516 2446 0 0
T17 3799 3733 0 0
T18 647 500 0 0
T19 2143 2005 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 212405120 343295 0 0
T1 4034 3043 0 0
T2 1112 0 0 0
T3 1935 0 0 0
T4 886 196 0 0
T5 1563 554 0 0
T6 13174 0 0 0
T7 0 508 0 0
T9 0 1320 0 0
T10 0 925 0 0
T16 2516 0 0 0
T17 3799 0 0 0
T18 647 0 0 0
T19 2143 0 0 0
T26 0 1300 0 0
T38 0 4702 0 0
T39 0 906 0 0
T59 0 128 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
TotalCoveredPercent
Conditions161381.25
Logical161381.25
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T5,T18
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T4,T5

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT18,T19,T144
110Not Covered
111CoveredT1,T4,T5

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT107,T108,T147
101CoveredT1,T4,T5
110Not Covered
111CoveredT1,T9,T10

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T4,T5


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 212214300 307134 0 0
DepthKnown_A 212405120 212250097 0 0
RvalidKnown_A 212405120 212250097 0 0
WreadyKnown_A 212405120 212250097 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 212405120 352200 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 212214300 307134 0 0
T1 4034 3075 0 0
T2 1112 0 0 0
T3 1935 0 0 0
T4 163 0 0 0
T5 133 36 0 0
T6 13174 0 0 0
T7 0 148 0 0
T8 0 140 0 0
T9 0 1363 0 0
T10 0 940 0 0
T11 0 1707 0 0
T16 2516 0 0 0
T17 3799 0 0 0
T18 293 0 0 0
T19 469 0 0 0
T26 0 1310 0 0
T38 0 4705 0 0
T39 0 917 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 212405120 212250097 0 0
T1 4034 3960 0 0
T2 1112 1030 0 0
T3 1935 1865 0 0
T4 886 737 0 0
T5 1563 1425 0 0
T6 13174 12811 0 0
T16 2516 2446 0 0
T17 3799 3733 0 0
T18 647 500 0 0
T19 2143 2005 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 212405120 212250097 0 0
T1 4034 3960 0 0
T2 1112 1030 0 0
T3 1935 1865 0 0
T4 886 737 0 0
T5 1563 1425 0 0
T6 13174 12811 0 0
T16 2516 2446 0 0
T17 3799 3733 0 0
T18 647 500 0 0
T19 2143 2005 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 212405120 212250097 0 0
T1 4034 3960 0 0
T2 1112 1030 0 0
T3 1935 1865 0 0
T4 886 737 0 0
T5 1563 1425 0 0
T6 13174 12811 0 0
T16 2516 2446 0 0
T17 3799 3733 0 0
T18 647 500 0 0
T19 2143 2005 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 212405120 352200 0 0
T1 4034 3075 0 0
T2 1112 0 0 0
T3 1935 0 0 0
T4 886 185 0 0
T5 1563 574 0 0
T6 13174 0 0 0
T7 0 618 0 0
T9 0 1363 0 0
T10 0 940 0 0
T16 2516 0 0 0
T17 3799 0 0 0
T18 647 22 0 0
T19 2143 20 0 0
T26 0 1310 0 0
T106 0 7 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%