Group : tb.dut.u_edn_cov_if::edn_sw_cmd_sts_cg
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Group : tb.dut.u_edn_cov_if::edn_sw_cmd_sts_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
63.64 63.64 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_sw_cmd_sts_cg 63.64 1 100 1 64 64




Group Instance : edn_sw_cmd_sts_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
63.64 1 100 1 64 64




Summary for Group Instance edn_sw_cmd_sts_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 11 4 7 63.64


Variables for Group Instance edn_sw_cmd_sts_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_cmd_ack_cg 2 0 2 100.00 100 1 1 0
cp_cmd_rdy_cg 2 0 2 100.00 100 1 1 0
cp_cmd_reg_rdy_cg 2 0 2 100.00 100 1 1 0
cp_cmd_sts_cg 5 4 1 20.00 100 1 1 0


Summary for Variable cp_cmd_ack_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_cmd_ack_cg

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
no_ack 28625 1 T1 8 T3 35 T7 9
ack 22512 1 T1 9 T3 7 T7 5



Summary for Variable cp_cmd_rdy_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_cmd_rdy_cg

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_ready 27772 1 T1 7 T3 34 T7 9
ready 23365 1 T1 10 T3 8 T7 5



Summary for Variable cp_cmd_reg_rdy_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_cmd_reg_rdy_cg

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
not_ready 486 1 T7 1 T42 10 T43 9
ready 50651 1 T1 17 T3 42 T7 13



Summary for Variable cp_cmd_sts_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 4 1 20.00


Automatically Generated Bins for cp_cmd_sts_cg

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[CMD_STS_INVALID_ACMD] 0 1 1
auto[CMD_STS_INVALID_STATE_PARAM] 0 1 1
auto[CMD_STS_INVALID_GEN_CMD] 0 1 1
auto[CMD_STS_UNDRIVEN] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[CMD_STS_SUCCESS] 51137 1 T1 17 T3 42 T7 14

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