Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	791371	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6618924

1

T1

20

T2

2

T3

47

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1942424	1			T1	115		T2	1		T3	80
values[0x0]	2528600	1			T1	7		T2	4		T3	20
values[0x1]	2939271	1			T1	11		T3	24		T7	21

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	385708	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

7024587

1

T1

55

T2

2

T3

73

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29256	1			T7	1		T25	3		T42	727
valid_sources[0x01]	28565	1			T28	1		T42	514		T48	1
valid_sources[0x02]	29409	1			T1	1		T3	1		T42	549
valid_sources[0x03]	28885	1			T28	1		T42	762		T43	508
valid_sources[0x04]	29958	1			T3	1		T39	3		T42	550
valid_sources[0x05]	29651	1			T1	2		T3	1		T42	745
valid_sources[0x06]	30575	1			T42	627		T43	421		T155	6
valid_sources[0x07]	28885	1			T42	698		T43	840		T155	4
valid_sources[0x08]	29420	1			T3	1		T42	731		T48	1
valid_sources[0x09]	27959	1			T3	1		T4	1		T42	663
valid_sources[0x0a]	29901	1			T1	1		T3	1		T42	598
valid_sources[0x0b]	29992	1			T1	3		T42	634		T48	2
valid_sources[0x0c]	28220	1			T1	5		T3	2		T42	676
valid_sources[0x0d]	27883	1			T7	3		T28	1		T42	671
valid_sources[0x0e]	28886	1			T3	1		T42	657		T43	577
valid_sources[0x0f]	27196	1			T7	2		T27	1		T42	845
valid_sources[0x10]	29801	1			T25	13		T42	656		T48	1
valid_sources[0x11]	28241	1			T42	715		T43	973		T76	3
valid_sources[0x12]	31362	1			T42	652		T43	690		T155	1
valid_sources[0x13]	29252	1			T3	1		T42	725		T43	726
valid_sources[0x14]	29887	1			T42	560		T43	880		T155	9
valid_sources[0x15]	30459	1			T3	1		T4	1		T42	723
valid_sources[0x16]	26862	1			T42	617		T43	356		T155	8
valid_sources[0x17]	30056	1			T7	1		T4	1		T42	632
valid_sources[0x18]	30153	1			T1	1		T42	675		T43	642
valid_sources[0x19]	28788	1			T6	2		T42	708		T43	388
valid_sources[0x1a]	27540	1			T1	4		T3	1		T28	1
valid_sources[0x1b]	29190	1			T3	1		T42	835		T43	429
valid_sources[0x1c]	28001	1			T7	2		T42	617		T58	44
valid_sources[0x1d]	28134	1			T3	1		T28	1		T42	617
valid_sources[0x1e]	28795	1			T42	706		T43	781		T155	3
valid_sources[0x1f]	29968	1			T42	694		T43	202		T155	3
valid_sources[0x20]	30121	1			T1	1		T3	1		T42	646
valid_sources[0x21]	29953	1			T42	700		T43	571		T155	6
valid_sources[0x22]	29315	1			T7	1		T4	5		T42	577
valid_sources[0x23]	30287	1			T1	2		T3	1		T7	1
valid_sources[0x24]	28461	1			T4	1		T42	786		T49	2
valid_sources[0x25]	29467	1			T27	1		T39	1		T42	636
valid_sources[0x26]	29258	1			T1	1		T3	1		T27	1
valid_sources[0x27]	29654	1			T3	1		T28	1		T42	621
valid_sources[0x28]	30829	1			T4	3		T42	776		T48	1
valid_sources[0x29]	27993	1			T27	1		T42	670		T43	892
valid_sources[0x2a]	29510	1			T25	7		T42	752		T43	516
valid_sources[0x2b]	31032	1			T4	2		T28	1		T42	758
valid_sources[0x2c]	29920	1			T7	2		T27	1		T28	1
valid_sources[0x2d]	29437	1			T3	1		T42	763		T48	1
valid_sources[0x2e]	29529	1			T1	1		T3	3		T4	3
valid_sources[0x2f]	28133	1			T3	1		T27	2		T42	748
valid_sources[0x30]	29087	1			T3	2		T7	1		T42	686
valid_sources[0x31]	29095	1			T7	1		T4	2		T5	642
valid_sources[0x32]	26530	1			T1	2		T7	3		T42	672
valid_sources[0x33]	28344	1			T28	1		T39	1		T42	651
valid_sources[0x34]	28118	1			T3	1		T7	1		T6	1
valid_sources[0x35]	27720	1			T42	737		T43	373		T155	4
valid_sources[0x36]	28041	1			T42	635		T43	511		T155	10
valid_sources[0x37]	27905	1			T3	2		T42	593		T43	333
valid_sources[0x38]	28743	1			T42	681		T43	571		T155	1
valid_sources[0x39]	28318	1			T1	6		T3	1		T42	660
valid_sources[0x3a]	29579	1			T28	1		T42	726		T43	281
valid_sources[0x3b]	31133	1			T27	3		T28	1		T42	819
valid_sources[0x3c]	27964	1			T28	1		T42	726		T43	206
valid_sources[0x3d]	31157	1			T3	1		T42	585		T48	2
valid_sources[0x3e]	28317	1			T42	542		T43	500		T155	6
valid_sources[0x3f]	30703	1			T1	1		T4	1		T25	7
valid_sources[0x40]	27240	1			T1	1		T3	1		T25	4
valid_sources[0x41]	29697	1			T1	5		T3	1		T27	1
valid_sources[0x42]	28379	1			T7	1		T25	2		T39	1
valid_sources[0x43]	31839	1			T3	1		T42	611		T48	1
valid_sources[0x44]	28841	1			T3	3		T4	2		T28	1
valid_sources[0x45]	27959	1			T3	1		T42	550		T45	1
valid_sources[0x46]	27524	1			T42	768		T43	873		T155	2
valid_sources[0x47]	29479	1			T28	1		T42	751		T43	982
valid_sources[0x48]	29054	1			T1	1		T42	621		T43	374
valid_sources[0x49]	28044	1			T28	1		T42	648		T43	551
valid_sources[0x4a]	28001	1			T42	629		T48	1		T43	497
valid_sources[0x4b]	31464	1			T3	1		T7	1		T42	580
valid_sources[0x4c]	28691	1			T7	2		T42	739		T43	391
valid_sources[0x4d]	28581	1			T28	1		T42	762		T48	1
valid_sources[0x4e]	30074	1			T3	1		T7	1		T42	596
valid_sources[0x4f]	28523	1			T1	3		T3	2		T42	758
valid_sources[0x50]	29132	1			T7	2		T27	3		T42	651
valid_sources[0x51]	28840	1			T1	1		T28	1		T42	684
valid_sources[0x52]	28523	1			T1	4		T3	2		T7	2
valid_sources[0x53]	29608	1			T3	1		T42	744		T43	299
valid_sources[0x54]	29795	1			T7	1		T42	659		T43	787
valid_sources[0x55]	26825	1			T7	1		T27	3		T42	649
valid_sources[0x56]	27922	1			T3	2		T7	1		T28	2
valid_sources[0x57]	27759	1			T3	2		T4	1		T28	1
valid_sources[0x58]	29591	1			T1	5		T28	1		T42	588
valid_sources[0x59]	29300	1			T42	592		T43	409		T155	4
valid_sources[0x5a]	28274	1			T42	712		T43	810		T44	724
valid_sources[0x5b]	29718	1			T3	1		T4	1		T42	605
valid_sources[0x5c]	28512	1			T7	1		T42	730		T43	378
valid_sources[0x5d]	28239	1			T42	704		T43	176		T155	3
valid_sources[0x5e]	27932	1			T42	750		T43	500		T44	574
valid_sources[0x5f]	27381	1			T42	711		T43	641		T155	1
valid_sources[0x60]	28437	1			T7	1		T4	5		T42	605
valid_sources[0x61]	27251	1			T27	2		T28	1		T39	1
valid_sources[0x62]	30074	1			T3	1		T42	666		T48	1
valid_sources[0x63]	28622	1			T1	2		T3	1		T27	1
valid_sources[0x64]	29509	1			T4	1		T42	712		T43	536
valid_sources[0x65]	30630	1			T42	731		T43	432		T155	1
valid_sources[0x66]	28478	1			T25	2		T42	751		T45	3
valid_sources[0x67]	30759	1			T39	2		T42	636		T48	2
valid_sources[0x68]	29901	1			T1	3		T3	1		T28	1
valid_sources[0x69]	29000	1			T1	2		T28	1		T42	796
valid_sources[0x6a]	27850	1			T28	1		T42	827		T43	401
valid_sources[0x6b]	28715	1			T3	1		T39	1		T42	615
valid_sources[0x6c]	29396	1			T3	2		T27	2		T42	769
valid_sources[0x6d]	27777	1			T3	1		T6	2		T42	575
valid_sources[0x6e]	30873	1			T27	8		T42	677		T43	962
valid_sources[0x6f]	29059	1			T1	1		T3	1		T42	707
valid_sources[0x70]	27727	1			T1	1		T42	625		T43	851
valid_sources[0x71]	28649	1			T1	2		T3	1		T4	2
valid_sources[0x72]	28591	1			T42	559		T43	670		T155	5
valid_sources[0x73]	28245	1			T39	1		T42	697		T43	595
valid_sources[0x74]	27666	1			T3	1		T27	8		T39	2
valid_sources[0x75]	29376	1			T3	1		T7	1		T42	505
valid_sources[0x76]	28742	1			T25	9		T42	721		T43	880
valid_sources[0x77]	28186	1			T7	1		T25	8		T42	709
valid_sources[0x78]	29421	1			T1	2		T42	616		T48	1
valid_sources[0x79]	28999	1			T25	4		T42	820		T43	969
valid_sources[0x7a]	29249	1			T3	1		T7	1		T42	757
valid_sources[0x7b]	30661	1			T1	2		T3	2		T42	700
valid_sources[0x7c]	28261	1			T27	5		T39	2		T42	638
valid_sources[0x7d]	30128	1			T3	1		T6	1		T42	836
valid_sources[0x7e]	29668	1			T25	2		T27	1		T42	798
valid_sources[0x7f]	29440	1			T1	1		T3	1		T42	672
valid_sources[0x80]	29575	1			T1	1		T42	724		T43	85

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1664723

1

T1

8

T3

6

T7

4

values[0x0]

all_enables

biggest_size

2478819

1

T1

3

T2

2

T3

18

values[0x1]

all_enables

biggest_size

2475382

1

T1

9

T3

23

T7

18