Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
65.62	65.62	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	65.62	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
65.62	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	22	30	57.69

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	22	30	57.69	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2563	1			T1	1		T7	1		T25	1
non_zero_bins[1]	1890	1			T3	3		T24	1		T25	2
zero	8609	1			T1	4		T2	2		T3	1

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	532	1			T3	1		T25	1		T5	3
uni	3688	1			T1	2		T3	1		T24	1
gen	3831	1			T1	1		T2	1		T3	1
res	812	1			T7	1		T42	9		T43	5
ins	4199	1			T1	2		T2	1		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8897

1

T1

3

T2

1

T3

3

mubi_true

4165

1

T1

2

T2

1

T3

1

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

36

1

T31

1

T33

1

T57

1

pass

13026

1

T1

5

T2

2

T3

4

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	22	30	57.69	22
Automatically Generated Cross Bins	52	22	30	57.69	22
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res , ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	12

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res , ins]	[zero]	[fail]	[mubi_true]	--	--	3

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	130	1			T25	1		T5	1		T42	5
upd	non_zero_bins[0]	pass	mubi_true	114	1			T5	1		T42	4		T43	4
upd	non_zero_bins[1]	pass	mubi_false	89	1			T43	3		T155	2		T195	1
upd	non_zero_bins[1]	pass	mubi_true	84	1			T3	1		T42	1		T43	1
upd	zero	pass	mubi_false	55	1			T42	3		T44	2		T197	1
upd	zero	pass	mubi_true	60	1			T5	1		T42	1		T48	1
uni	zero	fail	mubi_false	11	1			T31	1		T33	1		T57	1
uni	zero	pass	mubi_false	2738	1			T1	2		T3	1		T24	1
uni	zero	pass	mubi_true	939	1			T5	2		T28	1		T42	15
gen	non_zero_bins[0]	pass	mubi_false	436	1			T42	6		T43	5		T155	2
gen	non_zero_bins[0]	pass	mubi_true	460	1			T5	1		T42	8		T43	8
gen	non_zero_bins[1]	pass	mubi_false	331	1			T3	1		T27	1		T42	8
gen	non_zero_bins[1]	pass	mubi_true	329	1			T25	1		T5	2		T42	7
gen	zero	fail	mubi_false	14	1			T109	1		T110	1		T161	1
gen	zero	pass	mubi_false	1849	1			T2	1		T24	1		T5	3
gen	zero	pass	mubi_true	412	1			T1	1		T7	1		T5	1
res	non_zero_bins[0]	pass	mubi_false	173	1			T42	2		T77	4		T14	1
res	non_zero_bins[0]	pass	mubi_true	181	1			T42	4		T43	2		T155	2
res	non_zero_bins[1]	pass	mubi_false	159	1			T43	1		T44	1		T10	2
res	non_zero_bins[1]	pass	mubi_true	118	1			T42	1		T43	2		T44	1
res	zero	fail	mubi_false	6	1			T160	1		T231	1		T192	1
res	zero	pass	mubi_false	95	1			T42	1		T44	2		T77	3
res	zero	pass	mubi_true	80	1			T7	1		T42	1		T77	1
ins	non_zero_bins[0]	pass	mubi_false	522	1			T5	1		T42	15		T47	1
ins	non_zero_bins[0]	pass	mubi_true	547	1			T1	1		T7	1		T5	1
ins	non_zero_bins[1]	pass	mubi_false	377	1			T3	1		T24	1		T5	1
ins	non_zero_bins[1]	pass	mubi_true	403	1			T25	1		T5	1		T42	5
ins	zero	fail	mubi_false	5	1			T142	1		T232	1		T159	1
ins	zero	pass	mubi_false	1907	1			T1	1		T4	1		T5	3
ins	zero	pass	mubi_true	438	1			T2	1		T24	1		T5	2

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded