Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.67	100.00	100.00		73.33	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	94.67	100.00	100.00		73.33	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.67	100.00	100.00		73.33	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.67	100.00	100.00		73.33	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		106	106	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	102	102	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
77	1	1
78	1	1
81	1	1
82	1	1
			MISSING_ELSE
86	1	1
87	1	1
90	1	1
91	1	1
			MISSING_ELSE
95	1	1
98	1	1
99	1	1
			MISSING_ELSE
103	1	1
104	1	1
107	1	1
108	1	1
109	1	1
			MISSING_ELSE
114	1	1
115	1	1
116	1	1
			MISSING_ELSE
120	1	1
121	1	1
122	1	1
			MISSING_ELSE
126	1	1
127	1	1
128	1	1
			MISSING_ELSE
132	1	1
133	1	1
134	1	1
135	1	1
137	1	1
138	1	1
140	1	1
145	1	1
146	1	1
147	1	1
150	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
157	1	1
158	1	1
159	1	1
162	1	1
163	1	1
164	1	1
165	1	1
			MISSING_ELSE
169	1	1
172	1	1
175	1	1
183	1	1
184	1	1
186	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
207	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	14	14	100.00
Logical	14	14	100.00
Non-Logical	0	0
Event	0	0

 LINE       63
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T6,T49,T45
1	1	Covered	T2,T24,T6

 LINE       65
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T7
1	0	Covered	T4,T10,T14
1	1	Covered	T7,T4,T10

 LINE       183
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T31,T32,T33
1	0	Covered	T4,T6,T39

 LINE       184
 EXPRESSION (local_escalate_i ? Error : RejectCsrngEntropy)
             --------1-------

-1-	Status	Tests
0	Covered	T31,T32,T33
1	Covered	T4,T6,T39

 LINE       197
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T49

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	75	55	73.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	153	Covered	T7,T10,T14
AutoCaptGenCnt	140	Covered	T7,T10,T14
AutoCaptReseedCnt	138	Covered	T7,T10,T14
AutoDispatch	122	Covered	T7,T10,T14
AutoFirstAckWait	116	Covered	T7,T4,T10
AutoLoadIns	68	Covered	T7,T4,T10
AutoSendGenCmd	147	Covered	T7,T10,T14
AutoSendReseedCmd	159	Covered	T7,T10,T14
BootDone	95	Covered	T2,T24,T6
BootGenAckWait	87	Covered	T2,T24,T6
BootInsAckWait	78	Covered	T2,T24,T6
BootLoadGen	82	Covered	T2,T24,T6
BootLoadIns	64	Covered	T2,T24,T6
BootLoadUni	99	Covered	T24,T47,T46
BootPulse	91	Covered	T2,T24,T6
BootUniAckWait	104	Covered	T24,T47,T46
Error	184	Covered	T4,T6,T39
Idle	109	Covered	T1,T2,T3
RejectCsrngEntropy	184	Covered	T31,T32,T33
SWPortMode	73	Covered	T1,T3,T7

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	128	Covered	T7,T10,T14
AutoAckWait->Error	184	Covered	T9,T107,T108
AutoAckWait->Idle	207	Covered	T10,T14,T23
AutoAckWait->RejectCsrngEntropy	184	Covered	T32,T109,T110
AutoCaptGenCnt->AutoSendGenCmd	147	Covered	T7,T10,T14
AutoCaptGenCnt->Error	184	Covered	T111
AutoCaptGenCnt->Idle	207	Covered	T14,T112,T113
AutoCaptGenCnt->RejectCsrngEntropy	184	Not Covered
AutoCaptReseedCnt->AutoSendReseedCmd	159	Covered	T7,T10,T14
AutoCaptReseedCnt->Error	184	Covered	T114
AutoCaptReseedCnt->Idle	207	Covered	T115
AutoCaptReseedCnt->RejectCsrngEntropy	184	Not Covered
AutoDispatch->AutoCaptGenCnt	140	Covered	T7,T10,T14
AutoDispatch->AutoCaptReseedCnt	138	Covered	T7,T10,T14
AutoDispatch->Error	184	Covered	T8,T102,T116
AutoDispatch->Idle	135	Covered	T7,T100,T20
AutoDispatch->RejectCsrngEntropy	184	Not Covered
AutoFirstAckWait->AutoDispatch	122	Covered	T7,T10,T14
AutoFirstAckWait->Error	184	Covered	T4,T117
AutoFirstAckWait->Idle	207	Covered	T10,T118,T119
AutoFirstAckWait->RejectCsrngEntropy	184	Not Covered
AutoLoadIns->AutoFirstAckWait	116	Covered	T7,T4,T10
AutoLoadIns->Error	184	Covered	T60,T62,T120
AutoLoadIns->Idle	207	Covered	T4,T8,T33
AutoLoadIns->RejectCsrngEntropy	184	Not Covered
AutoSendGenCmd->AutoAckWait	153	Covered	T7,T10,T14
AutoSendGenCmd->Error	184	Covered	T121,T122
AutoSendGenCmd->Idle	207	Covered	T123,T124,T125
AutoSendGenCmd->RejectCsrngEntropy	184	Not Covered
AutoSendReseedCmd->AutoAckWait	165	Covered	T7,T10,T14
AutoSendReseedCmd->Error	184	Not Covered
AutoSendReseedCmd->Idle	207	Covered	T126,T127,T128
AutoSendReseedCmd->RejectCsrngEntropy	184	Not Covered
BootDone->BootLoadUni	99	Covered	T24,T47,T46
BootDone->Error	184	Covered	T6,T129,T130
BootDone->Idle	207	Covered	T49,T131,T132
BootDone->RejectCsrngEntropy	184	Not Covered
BootGenAckWait->BootPulse	91	Covered	T2,T24,T6
BootGenAckWait->Error	184	Covered	T63,T133,T134
BootGenAckWait->Idle	207	Covered	T45,T85,T63
BootGenAckWait->RejectCsrngEntropy	184	Covered	T135,T103,T136
BootInsAckWait->BootLoadGen	82	Covered	T2,T24,T6
BootInsAckWait->Error	184	Covered	T137,T138,T139
BootInsAckWait->Idle	207	Covered	T6,T80,T83
BootInsAckWait->RejectCsrngEntropy	184	Covered	T140,T141,T142
BootLoadGen->BootGenAckWait	87	Covered	T2,T24,T6
BootLoadGen->Error	184	Covered	T16,T64,T65
BootLoadGen->Idle	207	Covered	T143,T144,T145
BootLoadGen->RejectCsrngEntropy	184	Not Covered
BootLoadIns->BootInsAckWait	78	Covered	T2,T24,T6
BootLoadIns->Error	184	Covered	T146,T147,T148
BootLoadIns->Idle	207	Covered	T84,T71,T149
BootLoadIns->RejectCsrngEntropy	184	Not Covered
BootLoadUni->BootUniAckWait	104	Covered	T24,T47,T46
BootLoadUni->Error	184	Not Covered
BootLoadUni->Idle	207	Not Covered
BootLoadUni->RejectCsrngEntropy	184	Not Covered
BootPulse->BootDone	95	Covered	T2,T24,T6
BootPulse->Error	184	Covered	T150
BootPulse->Idle	207	Covered	T50,T151,T152
BootPulse->RejectCsrngEntropy	184	Not Covered
BootUniAckWait->Error	184	Not Covered
BootUniAckWait->Idle	109	Covered	T24,T47,T46
BootUniAckWait->RejectCsrngEntropy	184	Covered	T31,T33,T57
Error->RejectCsrngEntropy	184	Not Covered
Idle->AutoLoadIns	68	Covered	T7,T4,T10
Idle->BootLoadIns	64	Covered	T2,T24,T6
Idle->Error	184	Covered	T17,T18,T19
Idle->RejectCsrngEntropy	184	Not Covered
Idle->SWPortMode	73	Covered	T1,T3,T7
RejectCsrngEntropy->Error	184	Not Covered
RejectCsrngEntropy->Idle	207	Covered	T31,T32,T33
SWPortMode->Error	184	Covered	T39,T82,T15
SWPortMode->Idle	207	Covered	T5,T42,T43
SWPortMode->RejectCsrngEntropy	184	Not Covered

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
IF	42	2	2	100.00
CASE	61	35	35	100.00
IF	183	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	61	case (state_q)
-2-:	63	if ((boot_req_mode_i && edn_enable_i))
-3-:	65	if ((auto_req_mode_i && edn_enable_i))
-4-:	69	if (edn_enable_i)
-5-:	81	if (csrng_cmd_ack_i)
-6-:	90	if (csrng_cmd_ack_i)
-7-:	98	if ((!boot_req_mode_i))
-8-:	107	if (csrng_cmd_ack_i)
-9-:	115	if (sw_cmd_req_load_i)
-10-:	121	if (csrng_cmd_ack_i)
-11-:	127	if (csrng_cmd_ack_i)
-12-:	133	if ((!auto_req_mode_i))
-13-:	137	if (max_reqs_cnt_zero_i)
-14-:	152	if (cmd_sent_i)
-15-:	164	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T24,T6
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T4,T10
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T7
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T24,T6
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T2,T24,T6
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T2,T24,T6
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T24,T6
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T2,T24,T6
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T2,T24,T6
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T24,T6
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T47,T46
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T2,T6,T49
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T24,T47,T46
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T24,T47,T46
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T24,T47,T46
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T7,T4,T10
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T7,T4,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T7,T10,T14
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T7,T4,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T7,T10,T14
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T7,T10,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T7,T100,T20
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T7,T10,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T7,T10,T14
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T10,T14
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T7,T10,T14
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T7,T10,T14
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T10,T14
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T7,T10,T14
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T10,T14,T32
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T7
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T31,T32,T33
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T39
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T79,T80,T81

	LineNo.	Expression
-1-:	183	if ((local_escalate_i || csrng_ack_err_i))
-2-:	184	(local_escalate_i) ? 
-3-:	197	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T4,T6,T39
1	0	-	Covered	T31,T32,T33
0	-	1	Covered	T4,T6,T49
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	252892838	144126	0	0
FpvSecCmErrorStEscalate_A	252892838	145298	0	0
u_state_regs_A	252861385	252685303	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	144126	0	0
T4	1007	311	0	0
T5	16117	0	0	0
T6	798	360	0	0
T8	0	1096	0	0
T15	0	1111	0	0
T25	2435	0	0	0
T26	1669	0	0	0
T27	4597	0	0	0
T28	1076	0	0	0
T39	864	384	0	0
T42	809743	0	0	0
T58	2374	0	0	0
T79	0	1058	0	0
T80	0	1097	0	0
T81	0	1038	0	0
T82	0	1141	0	0
T83	0	229	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	145298	0	0
T4	1007	312	0	0
T5	16117	0	0	0
T6	798	361	0	0
T8	0	1097	0	0
T15	0	1112	0	0
T25	2435	0	0	0
T26	1669	0	0	0
T27	4597	0	0	0
T28	1076	0	0	0
T39	864	385	0	0
T42	809743	0	0	0
T58	2374	0	0	0
T79	0	1059	0	0
T80	0	1098	0	0
T81	0	1039	0	0
T82	0	1142	0	0
T83	0	230	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252861385	252685303	0	0
T1	2911	2837	0	0
T2	1241	1155	0	0
T3	5722	5664	0	0
T4	798	674	0	0
T5	16117	15633	0	0
T7	5330	5255	0	0
T24	1964	1897	0	0
T25	2435	2340	0	0
T26	1669	1569	0	0
T27	4597	4513	0	0