Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T4,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T36,T41
1	1	0	Not Covered
1	1	1	Covered	T7,T4,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T34,T38,T35
1	0	1	Covered	T7,T4,T6
1	1	0	Not Covered
1	1	1	Covered	T7,T10,T14

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T7,T4,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	505033878	956461	0	0
DepthKnown_A	505785676	505433512	0	0
RvalidKnown_A	505785676	505433512	0	0
WreadyKnown_A	505785676	505433512	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	505367060	1022993	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505033878	956461	0	0
T4	588	250	0	0
T5	32234	0	0	0
T6	234	0	0	0
T7	10660	7466	0	0
T8	0	254	0	0
T10	0	2602	0	0
T14	0	4414	0	0
T20	0	4495	0	0
T21	0	2666	0	0
T22	0	1581	0	0
T24	3928	0	0	0
T25	4870	0	0	0
T26	3338	0	0	0
T27	9194	0	0	0
T28	2152	0	0	0
T32	0	544	0	0
T39	530	0	0	0
T100	0	5684	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505785676	505433512	0	0
T1	5822	5674	0	0
T2	2482	2310	0	0
T3	11444	11328	0	0
T4	2014	1766	0	0
T5	32234	31266	0	0
T7	10660	10510	0	0
T24	3928	3794	0	0
T25	4870	4680	0	0
T26	3338	3138	0	0
T27	9194	9026	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505785676	505433512	0	0
T1	5822	5674	0	0
T2	2482	2310	0	0
T3	11444	11328	0	0
T4	2014	1766	0	0
T5	32234	31266	0	0
T7	10660	10510	0	0
T24	3928	3794	0	0
T25	4870	4680	0	0
T26	3338	3138	0	0
T27	9194	9026	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505785676	505433512	0	0
T1	5822	5674	0	0
T2	2482	2310	0	0
T3	11444	11328	0	0
T4	2014	1766	0	0
T5	32234	31266	0	0
T7	10660	10510	0	0
T24	3928	3794	0	0
T25	4870	4680	0	0
T26	3338	3138	0	0
T27	9194	9026	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	505367060	1022993	0	0
T4	2014	944	0	0
T5	32234	0	0	0
T6	1596	366	0	0
T7	10660	7466	0	0
T10	0	2602	0	0
T14	0	4414	0	0
T24	3928	0	0	0
T25	4870	0	0	0
T26	3338	0	0	0
T27	9194	0	0	0
T28	2152	0	0	0
T32	0	544	0	0
T39	1728	0	0	0
T80	0	358	0	0
T82	0	283	0	0
T83	0	271	0	0
T100	0	5684	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T101,T102,T103
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T4,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T41
1	1	0	Not Covered
1	1	1	Covered	T7,T4,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T34,T35,T104
1	0	1	Covered	T7,T4,T6
1	1	0	Not Covered
1	1	1	Covered	T7,T10,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T7,T4,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	252516939	473995	0	0
DepthKnown_A	252892838	252716756	0	0
RvalidKnown_A	252892838	252716756	0	0
WreadyKnown_A	252892838	252716756	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	252683530	507027	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252516939	473995	0	0
T4	294	106	0	0
T5	16117	0	0	0
T6	117	0	0	0
T7	5330	3668	0	0
T8	0	107	0	0
T10	0	1217	0	0
T14	0	2189	0	0
T20	0	2241	0	0
T21	0	1311	0	0
T22	0	768	0	0
T24	1964	0	0	0
T25	2435	0	0	0
T26	1669	0	0	0
T27	4597	0	0	0
T28	1076	0	0	0
T32	0	278	0	0
T39	265	0	0	0
T100	0	2828	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	252716756	0	0
T1	2911	2837	0	0
T2	1241	1155	0	0
T3	5722	5664	0	0
T4	1007	883	0	0
T5	16117	15633	0	0
T7	5330	5255	0	0
T24	1964	1897	0	0
T25	2435	2340	0	0
T26	1669	1569	0	0
T27	4597	4513	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	252716756	0	0
T1	2911	2837	0	0
T2	1241	1155	0	0
T3	5722	5664	0	0
T4	1007	883	0	0
T5	16117	15633	0	0
T7	5330	5255	0	0
T24	1964	1897	0	0
T25	2435	2340	0	0
T26	1669	1569	0	0
T27	4597	4513	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	252716756	0	0
T1	2911	2837	0	0
T2	1241	1155	0	0
T3	5722	5664	0	0
T4	1007	883	0	0
T5	16117	15633	0	0
T7	5330	5255	0	0
T24	1964	1897	0	0
T25	2435	2340	0	0
T26	1669	1569	0	0
T27	4597	4513	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	252683530	507027	0	0
T4	1007	424	0	0
T5	16117	0	0	0
T6	798	184	0	0
T7	5330	3668	0	0
T10	0	1217	0	0
T14	0	2189	0	0
T24	1964	0	0	0
T25	2435	0	0	0
T26	1669	0	0	0
T27	4597	0	0	0
T28	1076	0	0	0
T32	0	278	0	0
T39	864	0	0	0
T80	0	186	0	0
T82	0	147	0	0
T83	0	139	0	0
T100	0	2828	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T4,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T7,T4,T6

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T36
1	1	0	Not Covered
1	1	1	Covered	T7,T4,T6

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T38,T105,T106
1	0	1	Covered	T7,T4,T6
1	1	0	Not Covered
1	1	1	Covered	T7,T10,T14

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T7,T4,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	252516939	482466	0	0
DepthKnown_A	252892838	252716756	0	0
RvalidKnown_A	252892838	252716756	0	0
WreadyKnown_A	252892838	252716756	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	252683530	515966	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252516939	482466	0	0
T4	294	144	0	0
T5	16117	0	0	0
T6	117	0	0	0
T7	5330	3798	0	0
T8	0	147	0	0
T10	0	1385	0	0
T14	0	2225	0	0
T20	0	2254	0	0
T21	0	1355	0	0
T22	0	813	0	0
T24	1964	0	0	0
T25	2435	0	0	0
T26	1669	0	0	0
T27	4597	0	0	0
T28	1076	0	0	0
T32	0	266	0	0
T39	265	0	0	0
T100	0	2856	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	252716756	0	0
T1	2911	2837	0	0
T2	1241	1155	0	0
T3	5722	5664	0	0
T4	1007	883	0	0
T5	16117	15633	0	0
T7	5330	5255	0	0
T24	1964	1897	0	0
T25	2435	2340	0	0
T26	1669	1569	0	0
T27	4597	4513	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	252716756	0	0
T1	2911	2837	0	0
T2	1241	1155	0	0
T3	5722	5664	0	0
T4	1007	883	0	0
T5	16117	15633	0	0
T7	5330	5255	0	0
T24	1964	1897	0	0
T25	2435	2340	0	0
T26	1669	1569	0	0
T27	4597	4513	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	252716756	0	0
T1	2911	2837	0	0
T2	1241	1155	0	0
T3	5722	5664	0	0
T4	1007	883	0	0
T5	16117	15633	0	0
T7	5330	5255	0	0
T24	1964	1897	0	0
T25	2435	2340	0	0
T26	1669	1569	0	0
T27	4597	4513	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	252683530	515966	0	0
T4	1007	520	0	0
T5	16117	0	0	0
T6	798	182	0	0
T7	5330	3798	0	0
T10	0	1385	0	0
T14	0	2225	0	0
T24	1964	0	0	0
T25	2435	0	0	0
T26	1669	0	0	0
T27	4597	0	0	0
T28	1076	0	0	0
T32	0	266	0	0
T39	864	0	0	0
T80	0	172	0	0
T82	0	136	0	0
T83	0	132	0	0
T100	0	2856	0	0