Group : tb.dut.u_edn_cov_if::edn_cfg_cg
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Group : tb.dut.u_edn_cov_if::edn_cfg_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_cfg_cg 100.00 1 100 1 64 64




Group Instance : edn_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 21 0 21 100.00


Variables for Group Instance edn_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mode 3 0 3 100.00 100 1 1 0
cp_num_boot_reqs 2 0 2 100.00 100 1 1 0
cp_num_endpoints 7 0 7 100.00 100 1 1 8


Crosses for Group Instance edn_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_num_endpoints_mode 21 0 21 100.00 100 1 1 0


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_mode

Excluded/Illegal bins
NAMECOUNTSTATUS
both 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
boot_req_mode 141 1 T1 1 T26 1 T27 1
auto_req_mode 144 1 T2 1 T3 1 T18 1
sw_mode 2816 1 T20 1 T22 1 T4 45



Summary for Variable cp_num_boot_reqs

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
multiple 289 1 T1 1 T2 1 T3 1
single 107 1 T217 1 T26 1 T27 1



Summary for Variable cp_num_endpoints

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 7 0 7 100.00


Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1347 1 T2 1 T3 1 T20 1
auto[2] 145 1 T57 1 T271 1 T153 25
auto[3] 112 1 T19 1 T159 3 T272 1
auto[4] 141 1 T51 8 T273 1 T193 66
auto[5] 217 1 T76 1 T43 1 T274 8
auto[6] 114 1 T44 1 T79 1 T215 1
auto[7] 1025 1 T1 1 T4 45 T40 1



Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 21 0 21 100.00


Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins
cp_num_endpointscp_modeCOUNTSTATUS
[auto[0]] [boot_req_mode , auto_req_mode , sw_mode] -- Excluded (3 bins)


Covered bins
cp_num_endpointscp_modeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] boot_req_mode 88 1 T26 1 T27 1 T81 1
auto[1] auto_req_mode 93 1 T2 1 T3 1 T18 1
auto[1] sw_mode 1166 1 T20 1 T22 1 T74 1
auto[2] boot_req_mode 3 1 T275 1 T276 1 T277 1
auto[2] auto_req_mode 3 1 T278 1 T279 1 T280 1
auto[2] sw_mode 139 1 T57 1 T271 1 T153 25
auto[3] boot_req_mode 3 1 T272 1 T281 1 T282 1
auto[3] auto_req_mode 4 1 T19 1 T283 1 T284 1
auto[3] sw_mode 105 1 T159 3 T285 11 T221 11
auto[4] boot_req_mode 2 1 T273 1 T286 1 - -
auto[4] auto_req_mode 3 1 T287 1 T288 1 T289 1
auto[4] sw_mode 136 1 T51 8 T193 66 T290 1
auto[5] boot_req_mode 2 1 T291 1 T292 1 - -
auto[5] auto_req_mode 1 1 T293 1 - - - -
auto[5] sw_mode 214 1 T76 1 T43 1 T274 8
auto[6] boot_req_mode 4 1 T294 1 T295 1 T296 1
auto[6] auto_req_mode 2 1 T215 1 T297 1 - -
auto[6] sw_mode 108 1 T44 1 T79 1 T210 1
auto[7] boot_req_mode 39 1 T1 1 T46 1 T47 1
auto[7] auto_req_mode 38 1 T42 1 T10 1 T298 1
auto[7] sw_mode 948 1 T4 45 T40 1 T41 1

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