Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	622116	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4920659

1

T1

22

T2

52

T3

45

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1474442	1			T1	54		T2	30		T3	78
values[0x0]	1880057	1			T1	5		T2	29		T3	29
values[0x1]	2188276	1			T1	18		T2	25		T3	16

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	310120	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5232655

1

T1

40

T2

59

T3

67

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	22634	1			T1	1		T4	448		T40	2
valid_sources[0x01]	23148	1			T4	462		T40	1		T51	2
valid_sources[0x02]	21462	1			T1	1		T2	2		T4	460
valid_sources[0x03]	21776	1			T4	500		T40	3		T41	1
valid_sources[0x04]	21875	1			T2	1		T4	474		T40	1
valid_sources[0x05]	22193	1			T1	1		T2	2		T20	1
valid_sources[0x06]	22706	1			T4	470		T18	1		T40	1
valid_sources[0x07]	22153	1			T1	1		T4	521		T40	1
valid_sources[0x08]	21850	1			T4	472		T40	1		T42	2
valid_sources[0x09]	22037	1			T4	544		T40	4		T41	4
valid_sources[0x0a]	21415	1			T4	522		T18	1		T40	1
valid_sources[0x0b]	21443	1			T20	2		T21	1		T4	498
valid_sources[0x0c]	21702	1			T4	457		T18	4		T51	6
valid_sources[0x0d]	20944	1			T22	1		T4	469		T40	1
valid_sources[0x0e]	21284	1			T1	1		T4	463		T40	2
valid_sources[0x0f]	20434	1			T1	1		T4	490		T40	2
valid_sources[0x10]	20789	1			T4	477		T40	1		T51	2
valid_sources[0x11]	20813	1			T1	1		T4	459		T40	2
valid_sources[0x12]	19236	1			T1	1		T2	2		T4	466
valid_sources[0x13]	22361	1			T2	2		T4	527		T40	1
valid_sources[0x14]	21423	1			T21	2		T4	493		T40	4
valid_sources[0x15]	22515	1			T1	1		T4	455		T19	1
valid_sources[0x16]	22846	1			T1	1		T20	1		T4	475
valid_sources[0x17]	21914	1			T4	490		T40	7		T19	5
valid_sources[0x18]	20929	1			T4	488		T40	1		T37	31
valid_sources[0x19]	22116	1			T4	503		T40	1		T51	2
valid_sources[0x1a]	22646	1			T22	1		T4	508		T38	551
valid_sources[0x1b]	20142	1			T1	1		T4	472		T40	1
valid_sources[0x1c]	21915	1			T1	1		T2	1		T4	514
valid_sources[0x1d]	21627	1			T1	1		T4	473		T18	1
valid_sources[0x1e]	21938	1			T4	476		T40	1		T51	3
valid_sources[0x1f]	21886	1			T4	531		T40	2		T41	1
valid_sources[0x20]	21767	1			T1	1		T9	7		T4	472
valid_sources[0x21]	21847	1			T4	508		T40	2		T41	1
valid_sources[0x22]	21147	1			T2	1		T4	522		T40	2
valid_sources[0x23]	21832	1			T4	466		T51	4		T38	574
valid_sources[0x24]	21287	1			T1	1		T4	439		T40	3
valid_sources[0x25]	21267	1			T22	1		T4	484		T41	2
valid_sources[0x26]	21925	1			T1	1		T4	523		T40	2
valid_sources[0x27]	22511	1			T4	493		T40	2		T6	1
valid_sources[0x28]	22082	1			T1	1		T4	449		T40	1
valid_sources[0x29]	21180	1			T4	470		T18	3		T42	4
valid_sources[0x2a]	21669	1			T1	1		T2	1		T20	1
valid_sources[0x2b]	23752	1			T20	4		T4	539		T18	1
valid_sources[0x2c]	21661	1			T4	492		T40	2		T41	1
valid_sources[0x2d]	21063	1			T1	1		T4	510		T18	1
valid_sources[0x2e]	22144	1			T21	1		T4	497		T18	1
valid_sources[0x2f]	21395	1			T22	1		T4	487		T40	1
valid_sources[0x30]	21262	1			T4	499		T40	2		T41	1
valid_sources[0x31]	23138	1			T1	2		T4	557		T18	1
valid_sources[0x32]	21232	1			T4	494		T40	4		T41	1
valid_sources[0x33]	20996	1			T1	1		T2	3		T22	1
valid_sources[0x34]	21696	1			T22	1		T4	452		T18	1
valid_sources[0x35]	20674	1			T20	1		T21	1		T4	506
valid_sources[0x36]	21359	1			T22	1		T4	467		T40	2
valid_sources[0x37]	20862	1			T1	1		T22	1		T4	525
valid_sources[0x38]	22122	1			T4	518		T18	1		T41	2
valid_sources[0x39]	22760	1			T4	478		T41	2		T51	2
valid_sources[0x3a]	23046	1			T4	480		T40	6		T41	1
valid_sources[0x3b]	22079	1			T2	1		T22	3		T4	462
valid_sources[0x3c]	20554	1			T4	463		T41	2		T6	1
valid_sources[0x3d]	21469	1			T4	472		T40	1		T19	5
valid_sources[0x3e]	20273	1			T22	1		T4	497		T40	3
valid_sources[0x3f]	21866	1			T22	1		T4	474		T40	2
valid_sources[0x40]	21441	1			T4	471		T40	1		T41	1
valid_sources[0x41]	21664	1			T1	1		T4	440		T40	1
valid_sources[0x42]	22131	1			T2	3		T4	509		T41	1
valid_sources[0x43]	21983	1			T4	503		T40	3		T51	5
valid_sources[0x44]	22230	1			T22	1		T4	472		T18	1
valid_sources[0x45]	22976	1			T1	1		T20	2		T4	524
valid_sources[0x46]	22608	1			T1	1		T20	1		T4	495
valid_sources[0x47]	21653	1			T1	1		T4	483		T40	3
valid_sources[0x48]	21192	1			T9	24		T22	1		T4	477
valid_sources[0x49]	22085	1			T4	468		T6	1		T30	4
valid_sources[0x4a]	21671	1			T4	489		T40	1		T6	1
valid_sources[0x4b]	20205	1			T20	3		T4	430		T40	1
valid_sources[0x4c]	21874	1			T4	492		T41	2		T6	1
valid_sources[0x4d]	21261	1			T22	1		T4	520		T18	1
valid_sources[0x4e]	21239	1			T1	1		T2	1		T4	504
valid_sources[0x4f]	22929	1			T1	1		T2	1		T4	514
valid_sources[0x50]	21564	1			T20	2		T4	460		T40	3
valid_sources[0x51]	21047	1			T2	2		T4	508		T40	1
valid_sources[0x52]	22091	1			T21	1		T22	1		T4	459
valid_sources[0x53]	21561	1			T1	1		T4	524		T40	1
valid_sources[0x54]	22441	1			T4	508		T40	1		T51	1
valid_sources[0x55]	20818	1			T22	1		T4	453		T18	1
valid_sources[0x56]	22483	1			T1	1		T2	1		T4	479
valid_sources[0x57]	22272	1			T1	1		T4	499		T40	1
valid_sources[0x58]	19928	1			T4	477		T40	2		T51	1
valid_sources[0x59]	22916	1			T2	2		T4	467		T38	539
valid_sources[0x5a]	21245	1			T4	422		T18	7		T40	2
valid_sources[0x5b]	22781	1			T1	1		T4	441		T18	2
valid_sources[0x5c]	21383	1			T2	1		T4	437		T40	1
valid_sources[0x5d]	22398	1			T22	1		T4	502		T40	2
valid_sources[0x5e]	21656	1			T4	505		T40	1		T41	1
valid_sources[0x5f]	21446	1			T4	482		T40	4		T51	3
valid_sources[0x60]	21615	1			T22	1		T4	457		T40	2
valid_sources[0x61]	20537	1			T4	474		T40	1		T41	1
valid_sources[0x62]	21954	1			T4	517		T18	1		T40	1
valid_sources[0x63]	22438	1			T4	493		T41	1		T51	8
valid_sources[0x64]	21106	1			T4	482		T38	547		T10	5
valid_sources[0x65]	21590	1			T21	1		T22	1		T4	483
valid_sources[0x66]	20705	1			T2	1		T4	466		T40	1
valid_sources[0x67]	22789	1			T4	461		T18	3		T40	2
valid_sources[0x68]	21243	1			T4	440		T40	4		T51	5
valid_sources[0x69]	20782	1			T4	515		T40	4		T38	578
valid_sources[0x6a]	21129	1			T20	2		T4	519		T40	2
valid_sources[0x6b]	22243	1			T21	3		T4	537		T51	7
valid_sources[0x6c]	22149	1			T4	495		T40	2		T51	13
valid_sources[0x6d]	21573	1			T2	1		T4	534		T40	1
valid_sources[0x6e]	19960	1			T21	1		T4	492		T40	1
valid_sources[0x6f]	21032	1			T4	474		T18	1		T40	3
valid_sources[0x70]	20559	1			T4	476		T40	1		T51	1
valid_sources[0x71]	20695	1			T4	546		T40	2		T51	5
valid_sources[0x72]	22265	1			T4	514		T38	586		T10	5
valid_sources[0x73]	22614	1			T2	1		T4	519		T38	543
valid_sources[0x74]	22904	1			T1	1		T22	1		T4	508
valid_sources[0x75]	21390	1			T4	490		T40	2		T38	566
valid_sources[0x76]	21900	1			T4	466		T51	1		T217	1
valid_sources[0x77]	22355	1			T4	517		T40	4		T51	6
valid_sources[0x78]	20633	1			T2	2		T20	4		T22	1
valid_sources[0x79]	21814	1			T22	1		T4	471		T40	1
valid_sources[0x7a]	20790	1			T2	5		T4	485		T40	1
valid_sources[0x7b]	20782	1			T1	1		T4	504		T40	4
valid_sources[0x7c]	21704	1			T4	499		T18	1		T40	5
valid_sources[0x7d]	20406	1			T1	1		T4	480		T18	3
valid_sources[0x7e]	21137	1			T4	505		T51	17		T38	620
valid_sources[0x7f]	20922	1			T21	1		T22	1		T4	491
valid_sources[0x80]	23521	1			T2	1		T4	533		T40	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1240645

1

T1

5

T2

2

T3

4

values[0x0]

all_enables

biggest_size

1840048

1

T1

4

T2

27

T3

27

values[0x1]

all_enables

biggest_size

1839966

1

T1

13

T2

23

T3

14