Group : csrng_agent_pkg::device_cmd_cg
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Group : csrng_agent_pkg::device_cmd_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
65.62 65.62 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg 65.62 1 100 1 64 64




Group Instance : csrng_agent_pkg.csrng_device_cmd_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
65.62 1 100 1 64 64




Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 52 22 30 57.69


Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
csrng_clen_cp 3 0 3 100.00 100 1 1 0
csrng_cmd_cp 5 0 5 100.00 100 1 1 0
csrng_flag_cp 2 0 2 100.00 100 1 1 0
csrng_sts 2 0 2 100.00 100 1 1 0


Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
csrng_cmd_cross 52 22 30 57.69 100 1 1 0


Summary for Variable csrng_clen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for csrng_clen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
non_zero_bins[0] 2633 1 T1 3 T2 1 T3 3
non_zero_bins[1] 1844 1 T2 1 T3 3 T4 23
zero 8109 1 T1 4 T2 1 T3 2



Summary for Variable csrng_cmd_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
il 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
upd 495 1 T1 1 T22 1 T4 8
uni 3497 1 T1 2 T3 1 T20 1
gen 3797 1 T1 2 T2 1 T3 4
res 816 1 T2 1 T3 2 T4 6
ins 3981 1 T1 2 T2 1 T3 1



Summary for Variable csrng_flag_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_flag_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
mubi_false 8650 1 T1 4 T2 1 T3 6
mubi_true 3936 1 T1 3 T2 2 T3 2



Summary for Variable csrng_sts

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for csrng_sts

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
fail 41 1 T28 1 T29 1 T49 1
pass 12545 1 T1 7 T2 3 T3 8



Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 52 22 30 57.69 22
Automatically Generated Cross Bins 52 22 30 57.69 22
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for csrng_cmd_cross

Element holes
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTNUMBERSTATUS
[upd] * [fail] * -- -- 6
[gen , res , ins] [non_zero_bins[0] , non_zero_bins[1]] [fail] * -- -- 12


Uncovered bins
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTNUMBERSTATUS
[uni] [zero] [fail] [mubi_true] 0 1 1
[gen , res , ins] [zero] [fail] [mubi_true] -- -- 3


Covered bins
csrng_cmd_cpcsrng_clen_cpcsrng_stscsrng_flag_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
upd non_zero_bins[0] pass mubi_false 126 1 T1 1 T38 3 T154 1
upd non_zero_bins[0] pass mubi_true 117 1 T22 1 T4 1 T51 1
upd non_zero_bins[1] pass mubi_false 87 1 T4 4 T218 1 T38 2
upd non_zero_bins[1] pass mubi_true 76 1 T154 2 T39 2 T155 2
upd zero pass mubi_false 44 1 T4 1 T38 1 T80 1
upd zero pass mubi_true 45 1 T4 2 T154 1 T39 1
uni zero fail mubi_false 8 1 T149 1 T150 1 T151 1
uni zero pass mubi_false 2582 1 T1 2 T3 1 T20 1
uni zero pass mubi_true 907 1 T4 21 T51 1 T75 1
gen non_zero_bins[0] pass mubi_false 534 1 T4 5 T18 3 T19 3
gen non_zero_bins[0] pass mubi_true 446 1 T1 1 T3 1 T4 6
gen non_zero_bins[1] pass mubi_false 328 1 T2 1 T3 3 T4 5
gen non_zero_bins[1] pass mubi_true 309 1 T4 2 T18 1 T217 1
gen zero fail mubi_false 21 1 T28 1 T29 1 T49 1
gen zero pass mubi_false 1761 1 T1 1 T9 1 T20 1
gen zero pass mubi_true 398 1 T9 2 T22 1 T4 1
res non_zero_bins[0] pass mubi_false 187 1 T3 2 T4 1 T41 1
res non_zero_bins[0] pass mubi_true 195 1 T19 2 T38 4 T192 2
res non_zero_bins[1] pass mubi_false 119 1 T18 2 T51 1 T38 2
res non_zero_bins[1] pass mubi_true 153 1 T4 4 T38 3 T152 3
res zero fail mubi_false 7 1 T158 1 T191 1 T253 1
res zero pass mubi_false 84 1 T4 1 T38 1 T79 1
res zero pass mubi_true 71 1 T2 1 T74 1 T38 4
ins non_zero_bins[0] pass mubi_false 546 1 T4 8 T51 2 T38 16
ins non_zero_bins[0] pass mubi_true 482 1 T1 1 T2 1 T4 7
ins non_zero_bins[1] pass mubi_false 406 1 T4 4 T40 1 T41 1
ins non_zero_bins[1] pass mubi_true 366 1 T4 4 T51 1 T217 1
ins zero fail mubi_false 5 1 T132 1 T134 1 T254 1
ins zero pass mubi_false 1805 1 T9 1 T20 1 T22 1
ins zero pass mubi_true 371 1 T1 1 T3 1 T9 1


User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins
NAMECOUNTSTATUS
uni_clen 0 Excluded

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%