Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T31,T33,T84
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T34,T35,T36
1	0	1	Covered	T2,T3,T9
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T9

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	390661552	605277	0	0
DepthKnown_A	391454332	391077146	0	0
RvalidKnown_A	391454332	391077146	0	0
WreadyKnown_A	391454332	391077146	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	391028530	706635	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	390661552	605277	0	0
T2	9396	6773	0	0
T3	2514	703	0	0
T4	710816	0	0	0
T5	516	199	0	0
T7	0	485	0	0
T9	4824	467	0	0
T18	7322	1647	0	0
T19	0	2526	0	0
T20	3030	0	0	0
T21	2216	0	0	0
T22	2922	0	0	0
T28	0	574	0	0
T29	0	442	0	0
T40	3388	0	0	0
T42	0	2983	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391454332	391077146	0	0
T1	4876	4758	0	0
T2	9396	9252	0	0
T3	2514	2332	0	0
T4	710816	710790	0	0
T5	3070	2782	0	0
T9	4824	4708	0	0
T18	7322	7134	0	0
T20	3030	2852	0	0
T21	2216	2052	0	0
T22	2922	2724	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391454332	391077146	0	0
T1	4876	4758	0	0
T2	9396	9252	0	0
T3	2514	2332	0	0
T4	710816	710790	0	0
T5	3070	2782	0	0
T9	4824	4708	0	0
T18	7322	7134	0	0
T20	3030	2852	0	0
T21	2216	2052	0	0
T22	2922	2724	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391454332	391077146	0	0
T1	4876	4758	0	0
T2	9396	9252	0	0
T3	2514	2332	0	0
T4	710816	710790	0	0
T5	3070	2782	0	0
T9	4824	4708	0	0
T18	7322	7134	0	0
T20	3030	2852	0	0
T21	2216	2052	0	0
T22	2922	2724	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	391028530	706635	0	0
T2	9396	6773	0	0
T3	2514	703	0	0
T4	710816	0	0	0
T5	3070	1358	0	0
T6	0	276	0	0
T7	0	1894	0	0
T9	4824	467	0	0
T18	7322	1647	0	0
T19	0	2526	0	0
T20	3030	0	0	0
T21	2216	0	0	0
T22	2922	0	0	0
T28	0	574	0	0
T40	3388	0	0	0
T42	0	2983	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T15,T85
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T84,T86
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T35
1	0	1	Covered	T2,T3,T9
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T18

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	195330776	297646	0	0
DepthKnown_A	195727166	195538573	0	0
RvalidKnown_A	195727166	195538573	0	0
WreadyKnown_A	195727166	195538573	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	195514265	348243	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195330776	297646	0	0
T2	4698	3337	0	0
T3	1257	346	0	0
T4	355408	0	0	0
T5	258	73	0	0
T7	0	216	0	0
T9	2412	235	0	0
T18	3661	820	0	0
T19	0	1244	0	0
T20	1515	0	0	0
T21	1108	0	0	0
T22	1461	0	0	0
T28	0	297	0	0
T29	0	224	0	0
T40	1694	0	0	0
T42	0	1453	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195727166	195538573	0	0
T1	2438	2379	0	0
T2	4698	4626	0	0
T3	1257	1166	0	0
T4	355408	355395	0	0
T5	1535	1391	0	0
T9	2412	2354	0	0
T18	3661	3567	0	0
T20	1515	1426	0	0
T21	1108	1026	0	0
T22	1461	1362	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195727166	195538573	0	0
T1	2438	2379	0	0
T2	4698	4626	0	0
T3	1257	1166	0	0
T4	355408	355395	0	0
T5	1535	1391	0	0
T9	2412	2354	0	0
T18	3661	3567	0	0
T20	1515	1426	0	0
T21	1108	1026	0	0
T22	1461	1362	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195727166	195538573	0	0
T1	2438	2379	0	0
T2	4698	4626	0	0
T3	1257	1166	0	0
T4	355408	355395	0	0
T5	1535	1391	0	0
T9	2412	2354	0	0
T18	3661	3567	0	0
T20	1515	1426	0	0
T21	1108	1026	0	0
T22	1461	1362	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	195514265	348243	0	0
T2	4698	3337	0	0
T3	1257	346	0	0
T4	355408	0	0	0
T5	1535	620	0	0
T6	0	142	0	0
T7	0	915	0	0
T9	2412	235	0	0
T18	3661	820	0	0
T19	0	1244	0	0
T20	1515	0	0	0
T21	1108	0	0	0
T22	1461	0	0	0
T28	0	297	0	0
T40	1694	0	0	0
T42	0	1453	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T3,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T31,T87,T88
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T34,T36,T89
1	0	1	Covered	T2,T3,T9
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T9

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	195330776	307631	0	0
DepthKnown_A	195727166	195538573	0	0
RvalidKnown_A	195727166	195538573	0	0
WreadyKnown_A	195727166	195538573	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	195514265	358392	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195330776	307631	0	0
T2	4698	3436	0	0
T3	1257	357	0	0
T4	355408	0	0	0
T5	258	126	0	0
T7	0	269	0	0
T9	2412	232	0	0
T18	3661	827	0	0
T19	0	1282	0	0
T20	1515	0	0	0
T21	1108	0	0	0
T22	1461	0	0	0
T28	0	277	0	0
T29	0	218	0	0
T40	1694	0	0	0
T42	0	1530	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195727166	195538573	0	0
T1	2438	2379	0	0
T2	4698	4626	0	0
T3	1257	1166	0	0
T4	355408	355395	0	0
T5	1535	1391	0	0
T9	2412	2354	0	0
T18	3661	3567	0	0
T20	1515	1426	0	0
T21	1108	1026	0	0
T22	1461	1362	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195727166	195538573	0	0
T1	2438	2379	0	0
T2	4698	4626	0	0
T3	1257	1166	0	0
T4	355408	355395	0	0
T5	1535	1391	0	0
T9	2412	2354	0	0
T18	3661	3567	0	0
T20	1515	1426	0	0
T21	1108	1026	0	0
T22	1461	1362	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	195727166	195538573	0	0
T1	2438	2379	0	0
T2	4698	4626	0	0
T3	1257	1166	0	0
T4	355408	355395	0	0
T5	1535	1391	0	0
T9	2412	2354	0	0
T18	3661	3567	0	0
T20	1515	1426	0	0
T21	1108	1026	0	0
T22	1461	1362	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	195514265	358392	0	0
T2	4698	3436	0	0
T3	1257	357	0	0
T4	355408	0	0	0
T5	1535	738	0	0
T6	0	134	0	0
T7	0	979	0	0
T9	2412	232	0	0
T18	3661	827	0	0
T19	0	1282	0	0
T20	1515	0	0	0
T21	1108	0	0	0
T22	1461	0	0	0
T28	0	277	0	0
T40	1694	0	0	0
T42	0	1530	0	0