Module Definition
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Module Instance : tb.dut.u_edn_core.u_prim_count_max_reqs_cntr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.79 70.79


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
70.79 70.79


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.58 100.00 90.30 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 gen_normal_fifo.u_fifo_cnt


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_count ( parameter Width=32,ResetValue=0,EnableAlertTriggerSVA=1,DecrNeverTrue=0,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
70.79 70.79
tb.dut.u_edn_core.u_prim_count_max_reqs_cntr

TotalCoveredPercent
Totals 8 7 87.50
Total Bits 202 143 70.79
Total Bits 0->1 101 73 72.28
Total Bits 1->0 101 70 69.31

Ports 8 7 87.50
Port Bits 202 143 70.79
Port Bits 0->1 101 73 72.28
Port Bits 1->0 101 70 69.31

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_cnt_i[0] Yes Yes *T5,*T7,*T8 Yes T2,T3,T9 INPUT
set_cnt_i[3:1] No No Yes T10,T11,T12 INPUT
set_cnt_i[31:4] No No No INPUT
incr_en_i Unreachable Unreachable Unreachable INPUT
decr_en_i Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT
step_i[31:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[31:0] Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
cnt_after_commit_o[31:0] Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
err_o Yes Yes T8,T13,T14 Yes T8,T13,T14 OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Module : prim_count ( parameter Width=5,ResetValue=0,EnableAlertTriggerSVA=1,DecrNeverTrue=0,NumCnt=2 )
Toggle Coverage for Module self-instances :
SCORETOGGLE
100.00 100.00
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

SCORETOGGLE
100.00 100.00
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

SCORETOGGLE
100.00 100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr

SCORETOGGLE
100.00 100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr

TotalCoveredPercent
Totals 9 9 100.00
Total Bits 34 34 100.00
Total Bits 0->1 17 17 100.00
Total Bits 1->0 17 17 100.00

Ports 9 9 100.00
Port Bits 34 34 100.00
Port Bits 0->1 17 17 100.00
Port Bits 1->0 17 17 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Yes Yes T2,T3,T5 Yes T2,T3,T5 INPUT
set_cnt_i[3:0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[4] Yes Yes T2,T3,T5 Yes T2,T3,T5 INPUT
incr_en_i Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[4:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[4:0] Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
cnt_after_commit_o[4:0] Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
err_o Yes Yes T15,T16,T17 Yes T15,T16,T17 OUTPUT

Toggle Coverage for Instance : tb.dut.u_edn_core.u_prim_count_max_reqs_cntr
TotalCoveredPercent
Totals 8 7 87.50
Total Bits 202 143 70.79
Total Bits 0->1 101 73 72.28
Total Bits 1->0 101 70 69.31

Ports 8 7 87.50
Port Bits 202 143 70.79
Port Bits 0->1 101 73 72.28
Port Bits 1->0 101 70 69.31

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
clr_i Unreachable Unreachable Unreachable INPUT
set_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_cnt_i[0] Yes Yes *T5,*T7,*T8 Yes T2,T3,T9 INPUT
set_cnt_i[3:1] No No Yes T10,T11,T12 INPUT
set_cnt_i[31:4] No No No INPUT
incr_en_i Unreachable Unreachable Unreachable INPUT
decr_en_i Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT
step_i[31:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[31:0] Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
cnt_after_commit_o[31:0] Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
err_o Yes Yes T8,T13,T14 Yes T8,T13,T14 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr
TotalCoveredPercent
Totals 9 9 100.00
Total Bits 34 34 100.00
Total Bits 0->1 17 17 100.00
Total Bits 1->0 17 17 100.00

Ports 9 9 100.00
Port Bits 34 34 100.00
Port Bits 0->1 17 17 100.00
Port Bits 1->0 17 17 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Yes Yes T3,T18,T19 Yes T3,T18,T19 INPUT
set_cnt_i[3:0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[4] Yes Yes T3,T18,T19 Yes T3,T18,T19 INPUT
incr_en_i Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[4:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[4:0] Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
cnt_after_commit_o[4:0] Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
err_o Yes Yes T15,T16,T17 Yes T15,T16,T17 OUTPUT

Toggle Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr
TotalCoveredPercent
Totals 9 9 100.00
Total Bits 34 34 100.00
Total Bits 0->1 17 17 100.00
Total Bits 1->0 17 17 100.00

Ports 9 9 100.00
Port Bits 34 34 100.00
Port Bits 0->1 17 17 100.00
Port Bits 1->0 17 17 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Yes Yes T3,T18,T19 Yes T3,T18,T19 INPUT
set_cnt_i[3:0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[4] Yes Yes T3,T18,T19 Yes T3,T18,T19 INPUT
incr_en_i Yes Yes T2,T3,T18 Yes T2,T3,T18 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[4:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[4:0] Yes Yes T2,T3,T18 Yes T2,T3,T18 OUTPUT
cnt_after_commit_o[4:0] Yes Yes T2,T3,T18 Yes T2,T3,T18 OUTPUT
err_o Yes Yes T15,T16,T17 Yes T15,T16,T17 OUTPUT

Toggle Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_wptr
TotalCoveredPercent
Totals 9 9 100.00
Total Bits 34 34 100.00
Total Bits 0->1 17 17 100.00
Total Bits 1->0 17 17 100.00

Ports 9 9 100.00
Port Bits 34 34 100.00
Port Bits 0->1 17 17 100.00
Port Bits 1->0 17 17 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Yes Yes T2,T3,T5 Yes T2,T3,T5 INPUT
set_cnt_i[3:0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[4] Yes Yes T2,T3,T5 Yes T2,T3,T5 INPUT
incr_en_i Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[4:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[4:0] Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
cnt_after_commit_o[4:0] Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
err_o Yes Yes T15,T16,T17 Yes T15,T16,T17 OUTPUT

Toggle Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt.gen_secure_ptrs.u_rptr
TotalCoveredPercent
Totals 9 9 100.00
Total Bits 34 34 100.00
Total Bits 0->1 17 17 100.00
Total Bits 1->0 17 17 100.00

Ports 9 9 100.00
Port Bits 34 34 100.00
Port Bits 0->1 17 17 100.00
Port Bits 1->0 17 17 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
clr_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
set_i Yes Yes T2,T3,T18 Yes T2,T3,T18 INPUT
set_cnt_i[3:0] Unreachable Unreachable Unreachable INPUT
set_cnt_i[4] Yes Yes T2,T3,T18 Yes T2,T3,T18 INPUT
incr_en_i Yes Yes T2,T3,T9 Yes T2,T3,T9 INPUT
decr_en_i Unreachable Unreachable Unreachable INPUT
step_i[4:0] Unreachable Unreachable Unreachable INPUT
commit_i Unreachable Unreachable Unreachable INPUT
cnt_o[4:0] Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
cnt_after_commit_o[4:0] Yes Yes T2,T3,T9 Yes T2,T3,T9 OUTPUT
err_o Yes Yes T15,T16,T17 Yes T15,T16,T17 OUTPUT

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