Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	609768	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4763236

1

T1

3

T2

8

T3

51

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1435333	1			T1	1		T2	20		T3	12
values[0x0]	1820231	1			T1	3		T2	4		T3	23
values[0x1]	2117440	1			T1	2		T2	6		T3	35

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	306456	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5066548

1

T1

3

T2

11

T3

59

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	20808	1			T19	218		T5	3		T17	1
valid_sources[0x01]	21367	1			T4	5		T20	2		T23	2
valid_sources[0x02]	21264	1			T4	1		T11	2		T17	2
valid_sources[0x03]	21649	1			T20	2		T17	5		T28	1
valid_sources[0x04]	20942	1			T11	4		T47	5		T27	3
valid_sources[0x05]	19082	1			T20	1		T11	1		T17	1
valid_sources[0x06]	21180	1			T4	6		T20	1		T23	1
valid_sources[0x07]	21522	1			T3	1		T20	1		T21	1
valid_sources[0x08]	23853	1			T11	1		T28	1		T47	11
valid_sources[0x09]	20834	1			T20	1		T11	2		T47	2
valid_sources[0x0a]	20009	1			T4	1		T20	3		T17	1
valid_sources[0x0b]	20040	1			T11	1		T33	2		T43	1
valid_sources[0x0c]	21034	1			T20	2		T11	1		T64	1
valid_sources[0x0d]	22500	1			T20	1		T42	7		T67	1
valid_sources[0x0e]	22074	1			T17	3		T28	1		T47	5
valid_sources[0x0f]	19659	1			T2	1		T20	1		T22	80
valid_sources[0x10]	20752	1			T23	1		T11	3		T17	3
valid_sources[0x11]	20635	1			T20	1		T11	4		T47	5
valid_sources[0x12]	20241	1			T23	1		T17	1		T47	1
valid_sources[0x13]	21365	1			T23	1		T11	1		T64	6
valid_sources[0x14]	22068	1			T20	1		T11	1		T17	2
valid_sources[0x15]	21936	1			T4	6		T11	1		T47	3
valid_sources[0x16]	20950	1			T4	7		T20	1		T11	1
valid_sources[0x17]	20450	1			T20	1		T47	2		T69	1
valid_sources[0x18]	21050	1			T4	5		T47	4		T27	3
valid_sources[0x19]	23189	1			T47	5		T9	1		T14	5
valid_sources[0x1a]	20088	1			T17	1		T47	3		T27	1
valid_sources[0x1b]	19707	1			T20	2		T17	2		T28	1
valid_sources[0x1c]	21905	1			T11	4		T17	1		T47	1
valid_sources[0x1d]	19898	1			T23	1		T11	3		T17	3
valid_sources[0x1e]	20052	1			T11	3		T64	1		T17	1
valid_sources[0x1f]	22163	1			T4	2		T11	3		T17	1
valid_sources[0x20]	21326	1			T21	1		T28	2		T47	7
valid_sources[0x21]	21981	1			T17	3		T47	1		T44	9
valid_sources[0x22]	21075	1			T20	1		T11	1		T47	3
valid_sources[0x23]	21545	1			T4	9		T20	1		T11	1
valid_sources[0x24]	20721	1			T11	1		T17	1		T47	8
valid_sources[0x25]	22228	1			T20	1		T21	1		T11	2
valid_sources[0x26]	21583	1			T11	1		T5	1		T28	1
valid_sources[0x27]	21366	1			T2	2		T11	2		T17	1
valid_sources[0x28]	21001	1			T11	1		T17	4		T47	4
valid_sources[0x29]	19538	1			T11	4		T17	1		T44	4
valid_sources[0x2a]	19029	1			T21	1		T17	9		T47	4
valid_sources[0x2b]	20896	1			T20	2		T11	1		T47	1
valid_sources[0x2c]	22059	1			T47	1		T9	3		T44	2
valid_sources[0x2d]	20906	1			T2	1		T4	4		T20	1
valid_sources[0x2e]	20823	1			T11	1		T17	2		T47	5
valid_sources[0x2f]	19743	1			T11	3		T17	4		T47	3
valid_sources[0x30]	21989	1			T11	2		T17	3		T47	2
valid_sources[0x31]	21407	1			T20	5		T17	4		T47	3
valid_sources[0x32]	19979	1			T4	1		T17	4		T9	2
valid_sources[0x33]	19573	1			T11	3		T47	3		T44	1
valid_sources[0x34]	19430	1			T20	2		T11	1		T47	1
valid_sources[0x35]	18309	1			T3	2		T47	2		T9	2
valid_sources[0x36]	19409	1			T20	4		T17	3		T9	1
valid_sources[0x37]	20002	1			T20	3		T17	2		T28	1
valid_sources[0x38]	21156	1			T17	1		T9	1		T54	1
valid_sources[0x39]	19170	1			T3	4		T20	1		T17	4
valid_sources[0x3a]	22167	1			T23	1		T17	1		T28	1
valid_sources[0x3b]	22041	1			T47	6		T27	1		T67	3
valid_sources[0x3c]	20628	1			T21	2		T64	4		T47	1
valid_sources[0x3d]	20242	1			T20	1		T11	2		T17	2
valid_sources[0x3e]	20806	1			T20	2		T64	2		T27	1
valid_sources[0x3f]	21594	1			T20	2		T11	1		T17	4
valid_sources[0x40]	20188	1			T4	3		T23	1		T17	2
valid_sources[0x41]	20750	1			T2	1		T20	1		T17	4
valid_sources[0x42]	20596	1			T20	1		T11	1		T47	2
valid_sources[0x43]	22149	1			T20	2		T64	2		T47	6
valid_sources[0x44]	20176	1			T1	1		T5	9		T17	2
valid_sources[0x45]	20951	1			T4	2		T20	5		T11	2
valid_sources[0x46]	20578	1			T3	2		T47	2		T44	5
valid_sources[0x47]	20978	1			T11	3		T17	2		T47	4
valid_sources[0x48]	21179	1			T11	1		T17	1		T47	6
valid_sources[0x49]	19613	1			T3	1		T20	2		T47	1
valid_sources[0x4a]	19102	1			T23	1		T17	1		T47	1
valid_sources[0x4b]	19894	1			T11	1		T47	3		T9	2
valid_sources[0x4c]	20845	1			T17	1		T47	2		T27	3
valid_sources[0x4d]	21513	1			T11	1		T5	2		T17	6
valid_sources[0x4e]	19712	1			T21	1		T9	2		T42	1
valid_sources[0x4f]	20911	1			T2	1		T21	1		T11	2
valid_sources[0x50]	20447	1			T21	2		T11	2		T17	4
valid_sources[0x51]	21035	1			T20	1		T47	4		T9	2
valid_sources[0x52]	21219	1			T11	2		T17	1		T28	1
valid_sources[0x53]	21808	1			T17	1		T47	4		T9	2
valid_sources[0x54]	19942	1			T20	1		T23	1		T11	1
valid_sources[0x55]	21079	1			T4	5		T11	1		T5	2
valid_sources[0x56]	22655	1			T11	2		T27	1		T6	13
valid_sources[0x57]	21595	1			T2	1		T4	4		T20	3
valid_sources[0x58]	20002	1			T11	3		T17	1		T47	4
valid_sources[0x59]	21278	1			T20	1		T21	1		T47	9
valid_sources[0x5a]	21109	1			T4	3		T11	4		T17	4
valid_sources[0x5b]	19823	1			T20	1		T47	5		T67	1
valid_sources[0x5c]	19498	1			T3	7		T11	4		T5	10
valid_sources[0x5d]	19862	1			T4	18		T20	3		T64	1
valid_sources[0x5e]	21232	1			T11	2		T64	1		T47	6
valid_sources[0x5f]	19823	1			T11	1		T17	3		T47	3
valid_sources[0x60]	21545	1			T17	6		T9	1		T43	3
valid_sources[0x61]	19304	1			T20	2		T17	3		T47	3
valid_sources[0x62]	21196	1			T2	1		T20	2		T11	1
valid_sources[0x63]	20025	1			T2	1		T11	1		T64	1
valid_sources[0x64]	18624	1			T20	2		T11	2		T64	2
valid_sources[0x65]	21312	1			T3	12		T20	3		T11	2
valid_sources[0x66]	21356	1			T11	1		T17	3		T47	7
valid_sources[0x67]	20155	1			T17	2		T47	2		T69	1
valid_sources[0x68]	21555	1			T11	1		T17	2		T47	8
valid_sources[0x69]	21036	1			T4	2		T20	2		T28	1
valid_sources[0x6a]	21296	1			T11	3		T47	2		T27	8
valid_sources[0x6b]	21210	1			T3	7		T20	1		T47	4
valid_sources[0x6c]	22737	1			T17	2		T47	3		T9	1
valid_sources[0x6d]	20101	1			T11	1		T17	2		T47	1
valid_sources[0x6e]	19821	1			T2	1		T11	1		T47	1
valid_sources[0x6f]	20054	1			T2	1		T23	1		T11	2
valid_sources[0x70]	20968	1			T20	2		T11	2		T47	3
valid_sources[0x71]	20409	1			T17	4		T27	3		T42	1
valid_sources[0x72]	20691	1			T2	1		T11	1		T17	5
valid_sources[0x73]	21852	1			T17	3		T47	4		T27	3
valid_sources[0x74]	22217	1			T4	2		T20	1		T17	2
valid_sources[0x75]	23652	1			T20	2		T11	1		T17	2
valid_sources[0x76]	20166	1			T20	1		T11	4		T17	1
valid_sources[0x77]	21088	1			T3	9		T11	6		T28	2
valid_sources[0x78]	19211	1			T4	2		T64	1		T47	3
valid_sources[0x79]	21587	1			T2	2		T11	1		T17	1
valid_sources[0x7a]	21559	1			T20	1		T11	2		T6	3
valid_sources[0x7b]	20803	1			T4	1		T11	1		T65	4
valid_sources[0x7c]	22606	1			T20	1		T11	1		T17	3
valid_sources[0x7d]	20628	1			T11	3		T17	3		T28	1
valid_sources[0x7e]	21240	1			T20	1		T11	1		T17	3
valid_sources[0x7f]	19594	1			T20	2		T23	1		T64	3
valid_sources[0x80]	22337	1			T20	1		T5	1		T17	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1201054

1

T2

4

T4

23

T19

3

values[0x0]

all_enables

biggest_size

1781425

1

T1

3

T2

4

T3

21

values[0x1]

all_enables

biggest_size

1780757

1

T3

30

T4

31

T19

5