Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
67.19	67.19	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	67.19	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
67.19	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	21	31	59.62

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	21	31	59.62	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2611	1			T3	1		T4	3		T19	1
non_zero_bins[1]	1753	1			T3	1		T4	2		T20	1
zero	8429	1			T1	3		T2	2		T3	1

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	503	1			T48	2		T43	1		T240	1
uni	3630	1			T4	5		T19	1		T8	1
gen	3761	1			T1	1		T2	1		T4	3
res	774	1			T3	1		T8	2		T11	2
ins	4125	1			T1	2		T2	1		T3	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8675

1

T2

2

T3

1

T4

7

mubi_true

4118

1

T1

3

T3

2

T4

6

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

27

1

T28

1

T29

1

T46

1

pass

12766

1

T1

3

T2

2

T3

3

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	21	31	59.62	21
Automatically Generated Cross Bins	52	21	31	59.62	21
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	4

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	114	1			T48	1		T39	5		T40	1
upd	non_zero_bins[0]	pass	mubi_true	131	1			T240	1		T39	2		T40	4
upd	non_zero_bins[1]	pass	mubi_false	71	1			T39	4		T241	1		T41	1
upd	non_zero_bins[1]	pass	mubi_true	84	1			T48	1		T43	1		T39	2
upd	zero	pass	mubi_false	40	1			T39	3		T41	1		T141	2
upd	zero	pass	mubi_true	63	1			T39	3		T41	1		T141	1
uni	zero	fail	mubi_false	5	1			T136	1		T137	1		T185	1
uni	zero	pass	mubi_false	2657	1			T4	2		T19	1		T8	1
uni	zero	pass	mubi_true	968	1			T4	3		T47	3		T67	1
gen	non_zero_bins[0]	pass	mubi_false	435	1			T4	1		T47	1		T27	1
gen	non_zero_bins[0]	pass	mubi_true	474	1			T11	1		T17	2		T47	4
gen	non_zero_bins[1]	pass	mubi_false	333	1			T8	7		T22	1		T9	1
gen	non_zero_bins[1]	pass	mubi_true	285	1			T8	1		T48	1		T18	2
gen	zero	fail	mubi_false	12	1			T28	1		T149	1		T150	1
gen	zero	pass	mubi_false	1829	1			T2	1		T4	2		T23	1
gen	zero	pass	mubi_true	393	1			T1	1		T19	1		T28	2
res	non_zero_bins[0]	pass	mubi_false	163	1			T8	2		T47	1		T39	2
res	non_zero_bins[0]	pass	mubi_true	200	1			T11	2		T27	1		T9	2
res	non_zero_bins[1]	pass	mubi_false	127	1			T17	2		T39	2		T71	2
res	non_zero_bins[1]	pass	mubi_true	118	1			T3	1		T48	1		T39	1
res	zero	fail	mubi_false	4	1			T29	1		T242	1		T243	1
res	zero	pass	mubi_false	69	1			T44	1		T48	1		T40	1
res	zero	pass	mubi_true	93	1			T47	1		T39	4		T84	2
ins	non_zero_bins[0]	pass	mubi_false	537	1			T3	1		T4	1		T19	1
ins	non_zero_bins[0]	pass	mubi_true	557	1			T4	1		T9	1		T44	1
ins	non_zero_bins[1]	pass	mubi_false	371	1			T20	1		T22	1		T17	1
ins	non_zero_bins[1]	pass	mubi_true	364	1			T4	2		T27	1		T69	1
ins	zero	fail	mubi_false	4	1			T122	1		T244	1		T245	1
ins	zero	fail	mubi_true	2	1			T46	1		T246	1		-	-
ins	zero	pass	mubi_false	1904	1			T2	1		T4	1		T23	1
ins	zero	pass	mubi_true	386	1			T1	2		T3	1		T19	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded