Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.50	100.00	89.98			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.50	100.00	89.98			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.50	100.00	89.98			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.50	100.00	89.98			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.50	100.00	89.98			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.50	100.00	89.98			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.50	100.00	89.98			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T4
DataWait	75	Covered	T2,T3,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T5,T34
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T45,T133,T159
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T3,T4
DataWait->AckPls	80	Covered	T2,T3,T4
DataWait->Disabled	107	Covered	T1,T115,T84
DataWait->Error	99	Covered	T6,T14,T160
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T12,T15,T16
EndPointClear->Disabled	107	Covered	T54,T129,T161
EndPointClear->Error	99	Covered	T5,T12,T49
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T4
Idle->Disabled	107	Covered	T1,T3,T4
Idle->Error	99	Covered	T2,T34,T65

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T3,T4
Idle	-	1	0	-	Covered	T2,T3,T4
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T3,T4
DataWait	-	-	-	0	Covered	T3,T4,T19
AckPls	-	-	-	-	Covered	T2,T3,T4
Error	-	-	-	-	Covered	T2,T5,T34
default	-	-	-	-	Covered	T2,T12,T66

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T34
0	1	Covered	T1,T3,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1295011998	989598	0	0
FpvSecCmErrorStEscalate_A	1295011998	995989	0	0
u_state_regs_A	1294979678	1293898136	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1295011998	989598	0	0
T2	15400	7755	0	0
T3	22750	0	0	0
T4	52038	0	0	0
T5	0	4410	0	0
T6	0	4186	0	0
T8	23597	0	0	0
T11	24479	0	0	0
T12	0	50421	0	0
T13	0	1596	0	0
T14	0	2464	0	0
T19	17682	0	0	0
T20	39837	0	0	0
T21	9331	0	0	0
T22	13020	0	0	0
T23	11046	0	0	0
T34	0	4130	0	0
T65	0	1722	0	0
T66	0	2596	0	0
T68	0	2386	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1295011998	995989	0	0
T2	15400	7762	0	0
T3	22750	0	0	0
T4	52038	0	0	0
T5	0	4417	0	0
T6	0	4193	0	0
T8	23597	0	0	0
T11	24479	0	0	0
T12	0	51331	0	0
T13	0	1603	0	0
T14	0	2471	0	0
T19	17682	0	0	0
T20	39837	0	0	0
T21	9331	0	0	0
T22	13020	0	0	0
T23	11046	0	0	0
T34	0	4137	0	0
T65	0	1729	0	0
T66	0	2603	0	0
T68	0	2393	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1294979678	1293898136	0	0
T1	7399	6958	0	0
T2	15222	14179	0	0
T3	22750	22344	0	0
T4	52038	50204	0	0
T8	23597	22946	0	0
T19	17682	17241	0	0
T20	39837	39396	0	0
T21	9331	8666	0	0
T22	13020	12369	0	0
T23	11046	10423	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T20,T11,T17
DataWait	75	Covered	T20,T11,T17
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T5,T34
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T20,T11,T17
DataWait->AckPls	80	Covered	T20,T11,T17
DataWait->Disabled	107	Covered	T162,T163,T164
DataWait->Error	99	Covered	T6,T165,T166
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T12,T15,T16
EndPointClear->Disabled	107	Covered	T54,T129,T161
EndPointClear->Error	99	Covered	T5,T12,T49
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T20,T11,T17
Idle->Disabled	107	Covered	T1,T3,T4
Idle->Error	99	Covered	T2,T34,T65

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T20,T11,T17
Idle	-	1	0	-	Covered	T20,T11,T17
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T20,T11,T17
DataWait	-	-	-	0	Covered	T20,T11,T17
AckPls	-	-	-	-	Covered	T20,T11,T17
Error	-	-	-	-	Covered	T2,T5,T34
default	-	-	-	-	Covered	T12,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T34
0	1	Covered	T1,T3,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	185001714	141714	0	0
FpvSecCmErrorStEscalate_A	185001714	142627	0	0
u_state_regs_A	185001714	184847208	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	141714	0	0
T2	2200	1115	0	0
T3	3250	0	0	0
T4	7434	0	0	0
T5	0	630	0	0
T6	0	598	0	0
T8	3371	0	0	0
T11	3497	0	0	0
T12	0	7203	0	0
T13	0	228	0	0
T14	0	352	0	0
T19	2526	0	0	0
T20	5691	0	0	0
T21	1333	0	0	0
T22	1860	0	0	0
T23	1578	0	0	0
T34	0	590	0	0
T65	0	246	0	0
T66	0	378	0	0
T68	0	348	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	142627	0	0
T2	2200	1116	0	0
T3	3250	0	0	0
T4	7434	0	0	0
T5	0	631	0	0
T6	0	599	0	0
T8	3371	0	0	0
T11	3497	0	0	0
T12	0	7333	0	0
T13	0	229	0	0
T14	0	353	0	0
T19	2526	0	0	0
T20	5691	0	0	0
T21	1333	0	0	0
T22	1860	0	0	0
T23	1578	0	0	0
T34	0	591	0	0
T65	0	247	0	0
T66	0	379	0	0
T68	0	349	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	184847208	0	0
T1	1057	994	0	0
T2	2200	2051	0	0
T3	3250	3192	0	0
T4	7434	7172	0	0
T8	3371	3278	0	0
T19	2526	2463	0	0
T20	5691	5628	0	0
T21	1333	1238	0	0
T22	1860	1767	0	0
T23	1578	1489	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T20
DataWait	75	Covered	T2,T3,T20
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T5,T34
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T3,T20
DataWait->AckPls	80	Covered	T2,T3,T20
DataWait->Disabled	107	Covered	T87,T88,T167
DataWait->Error	99	Covered	T168,T169,T170
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T12,T15,T16
EndPointClear->Disabled	107	Covered	T54,T129,T161
EndPointClear->Error	99	Covered	T5,T12,T49
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T2,T3,T20
Idle->Disabled	107	Covered	T1,T3,T4
Idle->Error	99	Covered	T2,T34,T65

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T3,T20
Idle	-	1	0	-	Covered	T2,T3,T20
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T3,T20
DataWait	-	-	-	0	Covered	T3,T20,T17
AckPls	-	-	-	-	Covered	T2,T3,T20
Error	-	-	-	-	Covered	T2,T5,T34
default	-	-	-	-	Covered	T12,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T34
0	1	Covered	T1,T3,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	185001714	141714	0	0
FpvSecCmErrorStEscalate_A	185001714	142627	0	0
u_state_regs_A	185001714	184847208	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	141714	0	0
T2	2200	1115	0	0
T3	3250	0	0	0
T4	7434	0	0	0
T5	0	630	0	0
T6	0	598	0	0
T8	3371	0	0	0
T11	3497	0	0	0
T12	0	7203	0	0
T13	0	228	0	0
T14	0	352	0	0
T19	2526	0	0	0
T20	5691	0	0	0
T21	1333	0	0	0
T22	1860	0	0	0
T23	1578	0	0	0
T34	0	590	0	0
T65	0	246	0	0
T66	0	378	0	0
T68	0	348	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	142627	0	0
T2	2200	1116	0	0
T3	3250	0	0	0
T4	7434	0	0	0
T5	0	631	0	0
T6	0	599	0	0
T8	3371	0	0	0
T11	3497	0	0	0
T12	0	7333	0	0
T13	0	229	0	0
T14	0	353	0	0
T19	2526	0	0	0
T20	5691	0	0	0
T21	1333	0	0	0
T22	1860	0	0	0
T23	1578	0	0	0
T34	0	591	0	0
T65	0	247	0	0
T66	0	379	0	0
T68	0	349	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	184847208	0	0
T1	1057	994	0	0
T2	2200	2051	0	0
T3	3250	3192	0	0
T4	7434	7172	0	0
T8	3371	3278	0	0
T19	2526	2463	0	0
T20	5691	5628	0	0
T21	1333	1238	0	0
T22	1860	1767	0	0
T23	1578	1489	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T1,T20,T11
DataWait	75	Covered	T1,T20,T11
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T5,T34
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T1,T20,T11
DataWait->AckPls	80	Covered	T1,T20,T11
DataWait->Disabled	107	Covered	T1,T84,T171
DataWait->Error	99	Covered	T95,T120,T103
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T12,T15,T16
EndPointClear->Disabled	107	Covered	T54,T129,T161
EndPointClear->Error	99	Covered	T5,T12,T49
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T1,T20,T11
Idle->Disabled	107	Covered	T3,T4,T5
Idle->Error	99	Covered	T2,T34,T65

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T20,T11
Idle	-	1	0	-	Covered	T1,T20,T11
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T20,T11
DataWait	-	-	-	0	Covered	T1,T20,T11
AckPls	-	-	-	-	Covered	T1,T20,T11
Error	-	-	-	-	Covered	T2,T5,T34
default	-	-	-	-	Covered	T12,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T34
0	1	Covered	T1,T3,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	185001714	141714	0	0
FpvSecCmErrorStEscalate_A	185001714	142627	0	0
u_state_regs_A	185001714	184847208	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	141714	0	0
T2	2200	1115	0	0
T3	3250	0	0	0
T4	7434	0	0	0
T5	0	630	0	0
T6	0	598	0	0
T8	3371	0	0	0
T11	3497	0	0	0
T12	0	7203	0	0
T13	0	228	0	0
T14	0	352	0	0
T19	2526	0	0	0
T20	5691	0	0	0
T21	1333	0	0	0
T22	1860	0	0	0
T23	1578	0	0	0
T34	0	590	0	0
T65	0	246	0	0
T66	0	378	0	0
T68	0	348	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	142627	0	0
T2	2200	1116	0	0
T3	3250	0	0	0
T4	7434	0	0	0
T5	0	631	0	0
T6	0	599	0	0
T8	3371	0	0	0
T11	3497	0	0	0
T12	0	7333	0	0
T13	0	229	0	0
T14	0	353	0	0
T19	2526	0	0	0
T20	5691	0	0	0
T21	1333	0	0	0
T22	1860	0	0	0
T23	1578	0	0	0
T34	0	591	0	0
T65	0	247	0	0
T66	0	379	0	0
T68	0	349	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	184847208	0	0
T1	1057	994	0	0
T2	2200	2051	0	0
T3	3250	3192	0	0
T4	7434	7172	0	0
T8	3371	3278	0	0
T19	2526	2463	0	0
T20	5691	5628	0	0
T21	1333	1238	0	0
T22	1860	1767	0	0
T23	1578	1489	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T20,T22,T11
DataWait	75	Covered	T20,T22,T11
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T5,T34
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T20,T22,T11
DataWait->AckPls	80	Covered	T20,T22,T11
DataWait->Disabled	107	Covered	T56,T172,T173
DataWait->Error	99	Covered	T174,T131
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T12,T15,T16
EndPointClear->Disabled	107	Covered	T54,T129,T161
EndPointClear->Error	99	Covered	T5,T12,T49
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T20,T22,T11
Idle->Disabled	107	Covered	T1,T3,T4
Idle->Error	99	Covered	T2,T34,T65

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T20,T22,T11
Idle	-	1	0	-	Covered	T20,T22,T11
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T20,T22,T11
DataWait	-	-	-	0	Covered	T20,T22,T11
AckPls	-	-	-	-	Covered	T20,T22,T11
Error	-	-	-	-	Covered	T2,T5,T34
default	-	-	-	-	Covered	T12,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T34
0	1	Covered	T1,T3,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	185001714	141714	0	0
FpvSecCmErrorStEscalate_A	185001714	142627	0	0
u_state_regs_A	185001714	184847208	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	141714	0	0
T2	2200	1115	0	0
T3	3250	0	0	0
T4	7434	0	0	0
T5	0	630	0	0
T6	0	598	0	0
T8	3371	0	0	0
T11	3497	0	0	0
T12	0	7203	0	0
T13	0	228	0	0
T14	0	352	0	0
T19	2526	0	0	0
T20	5691	0	0	0
T21	1333	0	0	0
T22	1860	0	0	0
T23	1578	0	0	0
T34	0	590	0	0
T65	0	246	0	0
T66	0	378	0	0
T68	0	348	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	142627	0	0
T2	2200	1116	0	0
T3	3250	0	0	0
T4	7434	0	0	0
T5	0	631	0	0
T6	0	599	0	0
T8	3371	0	0	0
T11	3497	0	0	0
T12	0	7333	0	0
T13	0	229	0	0
T14	0	353	0	0
T19	2526	0	0	0
T20	5691	0	0	0
T21	1333	0	0	0
T22	1860	0	0	0
T23	1578	0	0	0
T34	0	591	0	0
T65	0	247	0	0
T66	0	379	0	0
T68	0	349	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	184847208	0	0
T1	1057	994	0	0
T2	2200	2051	0	0
T3	3250	3192	0	0
T4	7434	7172	0	0
T8	3371	3278	0	0
T19	2526	2463	0	0
T20	5691	5628	0	0
T21	1333	1238	0	0
T22	1860	1767	0	0
T23	1578	1489	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T20,T11,T17
DataWait	75	Covered	T20,T11,T17
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T5,T34
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T45
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T20,T11,T17
DataWait->AckPls	80	Covered	T20,T11,T17
DataWait->Disabled	107	Covered	T75,T175,T176
DataWait->Error	99	Not Covered
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T12,T15,T16
EndPointClear->Disabled	107	Covered	T54,T129,T161
EndPointClear->Error	99	Covered	T5,T12,T49
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T20,T11,T17
Idle->Disabled	107	Covered	T1,T3,T4
Idle->Error	99	Covered	T2,T34,T65

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T20,T11,T17
Idle	-	1	0	-	Covered	T20,T11,T17
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T20,T11,T17
DataWait	-	-	-	0	Covered	T20,T11,T17
AckPls	-	-	-	-	Covered	T20,T11,T17
Error	-	-	-	-	Covered	T2,T5,T34
default	-	-	-	-	Covered	T12,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T34
0	1	Covered	T1,T3,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	185001714	141714	0	0
FpvSecCmErrorStEscalate_A	185001714	142627	0	0
u_state_regs_A	185001714	184847208	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	141714	0	0
T2	2200	1115	0	0
T3	3250	0	0	0
T4	7434	0	0	0
T5	0	630	0	0
T6	0	598	0	0
T8	3371	0	0	0
T11	3497	0	0	0
T12	0	7203	0	0
T13	0	228	0	0
T14	0	352	0	0
T19	2526	0	0	0
T20	5691	0	0	0
T21	1333	0	0	0
T22	1860	0	0	0
T23	1578	0	0	0
T34	0	590	0	0
T65	0	246	0	0
T66	0	378	0	0
T68	0	348	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	142627	0	0
T2	2200	1116	0	0
T3	3250	0	0	0
T4	7434	0	0	0
T5	0	631	0	0
T6	0	599	0	0
T8	3371	0	0	0
T11	3497	0	0	0
T12	0	7333	0	0
T13	0	229	0	0
T14	0	353	0	0
T19	2526	0	0	0
T20	5691	0	0	0
T21	1333	0	0	0
T22	1860	0	0	0
T23	1578	0	0	0
T34	0	591	0	0
T65	0	247	0	0
T66	0	379	0	0
T68	0	349	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	184847208	0	0
T1	1057	994	0	0
T2	2200	2051	0	0
T3	3250	3192	0	0
T4	7434	7172	0	0
T8	3371	3278	0	0
T19	2526	2463	0	0
T20	5691	5628	0	0
T21	1333	1238	0	0
T22	1860	1767	0	0
T23	1578	1489	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T4,T19,T20
DataWait	75	Covered	T4,T19,T20
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T5,T34
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T159
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T4,T19,T20
DataWait->AckPls	80	Covered	T4,T19,T20
DataWait->Disabled	107	Covered	T115,T126,T177
DataWait->Error	99	Covered	T14,T160,T178
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T12,T15,T16
EndPointClear->Disabled	107	Covered	T54,T129,T161
EndPointClear->Error	99	Covered	T5,T12,T49
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T4,T19,T20
Idle->Disabled	107	Covered	T1,T3,T4
Idle->Error	99	Covered	T34,T65,T6

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T4,T19,T20
Idle	-	1	0	-	Covered	T4,T19,T20
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T4,T19,T20
DataWait	-	-	-	0	Covered	T4,T19,T20
AckPls	-	-	-	-	Covered	T4,T19,T20
Error	-	-	-	-	Covered	T2,T5,T34
default	-	-	-	-	Covered	T2,T12,T66

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T34
0	1	Covered	T1,T3,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	185001714	139314	0	0
FpvSecCmErrorStEscalate_A	185001714	140227	0	0
u_state_regs_A	184969394	184814888	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	139314	0	0
T2	2200	1065	0	0
T3	3250	0	0	0
T4	7434	0	0	0
T5	0	630	0	0
T6	0	598	0	0
T8	3371	0	0	0
T11	3497	0	0	0
T12	0	7203	0	0
T13	0	228	0	0
T14	0	352	0	0
T19	2526	0	0	0
T20	5691	0	0	0
T21	1333	0	0	0
T22	1860	0	0	0
T23	1578	0	0	0
T34	0	590	0	0
T65	0	246	0	0
T66	0	328	0	0
T68	0	298	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	140227	0	0
T2	2200	1066	0	0
T3	3250	0	0	0
T4	7434	0	0	0
T5	0	631	0	0
T6	0	599	0	0
T8	3371	0	0	0
T11	3497	0	0	0
T12	0	7333	0	0
T13	0	229	0	0
T14	0	353	0	0
T19	2526	0	0	0
T20	5691	0	0	0
T21	1333	0	0	0
T22	1860	0	0	0
T23	1578	0	0	0
T34	0	591	0	0
T65	0	247	0	0
T66	0	329	0	0
T68	0	299	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184969394	184814888	0	0
T1	1057	994	0	0
T2	2022	1873	0	0
T3	3250	3192	0	0
T4	7434	7172	0	0
T8	3371	3278	0	0
T19	2526	2463	0	0
T20	5691	5628	0	0
T21	1333	1238	0	0
T22	1860	1767	0	0
T23	1578	1489	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T5

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T20,T11,T17
DataWait	75	Covered	T20,T11,T17
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T1,T2,T3
Error	99	Covered	T2,T5,T34
Idle	68	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T133
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T20,T11,T17
DataWait->AckPls	80	Covered	T20,T11,T17
DataWait->Disabled	107	Covered	T105
DataWait->Error	99	Covered	T92,T179,T93
Disabled->EndPointClear	63	Covered	T1,T2,T3
Disabled->Error	99	Covered	T12,T15,T16
EndPointClear->Disabled	107	Covered	T54,T129,T161
EndPointClear->Error	99	Covered	T5,T12,T49
EndPointClear->Idle	68	Covered	T1,T2,T3
Idle->DataWait	75	Covered	T20,T11,T17
Idle->Disabled	107	Covered	T1,T3,T4
Idle->Error	99	Covered	T2,T34,T65

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T20,T11,T17
Idle	-	1	0	-	Covered	T20,T11,T17
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T20,T11,T17
DataWait	-	-	-	0	Covered	T20,T11,T17
AckPls	-	-	-	-	Covered	T20,T11,T17
Error	-	-	-	-	Covered	T2,T5,T34
default	-	-	-	-	Covered	T12,T15,T16

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T5,T34
0	1	Covered	T1,T3,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	185001714	141714	0	0
FpvSecCmErrorStEscalate_A	185001714	142627	0	0
u_state_regs_A	185001714	184847208	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	141714	0	0
T2	2200	1115	0	0
T3	3250	0	0	0
T4	7434	0	0	0
T5	0	630	0	0
T6	0	598	0	0
T8	3371	0	0	0
T11	3497	0	0	0
T12	0	7203	0	0
T13	0	228	0	0
T14	0	352	0	0
T19	2526	0	0	0
T20	5691	0	0	0
T21	1333	0	0	0
T22	1860	0	0	0
T23	1578	0	0	0
T34	0	590	0	0
T65	0	246	0	0
T66	0	378	0	0
T68	0	348	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	142627	0	0
T2	2200	1116	0	0
T3	3250	0	0	0
T4	7434	0	0	0
T5	0	631	0	0
T6	0	599	0	0
T8	3371	0	0	0
T11	3497	0	0	0
T12	0	7333	0	0
T13	0	229	0	0
T14	0	353	0	0
T19	2526	0	0	0
T20	5691	0	0	0
T21	1333	0	0	0
T22	1860	0	0	0
T23	1578	0	0	0
T34	0	591	0	0
T65	0	247	0	0
T66	0	379	0	0
T68	0	349	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	184847208	0	0
T1	1057	994	0	0
T2	2200	2051	0	0
T3	3250	3192	0	0
T4	7434	7172	0	0
T8	3371	3278	0	0
T19	2526	2463	0	0
T20	5691	5628	0	0
T21	1333	1238	0	0
T22	1860	1767	0	0
T23	1578	1489	0	0