Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	92.86	100.00	71.43			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.84	100.00	89.19	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.50	100.00	89.98			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.50	100.00	89.98			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T35,T36,T37
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T31,T38
1	0	1	Covered	T3,T8,T11
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T11

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	369375436	532456	0	0
DepthKnown_A	370003428	369694416	0	0
RvalidKnown_A	370003428	369694416	0	0
WreadyKnown_A	370003428	369694416	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	369732886	611313	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	369375436	532456	0	0
T3	6500	3386	0	0
T4	14868	0	0	0
T5	0	83	0	0
T6	0	186	0	0
T8	6742	1795	0	0
T9	0	1627	0	0
T11	6994	2634	0	0
T17	0	13185	0	0
T19	5052	0	0	0
T20	11382	0	0	0
T21	2666	0	0	0
T22	3720	0	0	0
T23	3156	0	0	0
T28	0	782	0	0
T29	0	591	0	0
T30	0	469	0	0
T64	2046	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370003428	369694416	0	0
T1	2114	1988	0	0
T2	4400	4102	0	0
T3	6500	6384	0	0
T4	14868	14344	0	0
T8	6742	6556	0	0
T19	5052	4926	0	0
T20	11382	11256	0	0
T21	2666	2476	0	0
T22	3720	3534	0	0
T23	3156	2978	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370003428	369694416	0	0
T1	2114	1988	0	0
T2	4400	4102	0	0
T3	6500	6384	0	0
T4	14868	14344	0	0
T8	6742	6556	0	0
T19	5052	4926	0	0
T20	11382	11256	0	0
T21	2666	2476	0	0
T22	3720	3534	0	0
T23	3156	2978	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	370003428	369694416	0	0
T1	2114	1988	0	0
T2	4400	4102	0	0
T3	6500	6384	0	0
T4	14868	14344	0	0
T8	6742	6556	0	0
T19	5052	4926	0	0
T20	11382	11256	0	0
T21	2666	2476	0	0
T22	3720	3534	0	0
T23	3156	2978	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	369732886	611313	0	0
T3	6500	3386	0	0
T4	14868	0	0	0
T5	0	920	0	0
T6	0	3240	0	0
T8	6742	1795	0	0
T9	0	1627	0	0
T11	6994	2634	0	0
T17	0	13185	0	0
T19	5052	0	0	0
T20	11382	0	0	0
T21	2666	0	0	0
T22	3720	0	0	0
T23	3156	0	0	0
T28	0	782	0	0
T34	0	220	0	0
T64	2046	0	0	0
T65	0	278	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T77,T78
1	0	1	Covered	T3,T8,T11
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	184687718	270778	0	0
DepthKnown_A	185001714	184847208	0	0
RvalidKnown_A	185001714	184847208	0	0
WreadyKnown_A	185001714	184847208	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	184866443	310308	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184687718	270778	0	0
T3	3250	1781	0	0
T4	7434	0	0	0
T5	0	50	0	0
T6	0	129	0	0
T8	3371	906	0	0
T9	0	857	0	0
T11	3497	1313	0	0
T17	0	6596	0	0
T19	2526	0	0	0
T20	5691	0	0	0
T21	1333	0	0	0
T22	1860	0	0	0
T23	1578	0	0	0
T28	0	400	0	0
T29	0	297	0	0
T30	0	228	0	0
T64	1023	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	184847208	0	0
T1	1057	994	0	0
T2	2200	2051	0	0
T3	3250	3192	0	0
T4	7434	7172	0	0
T8	3371	3278	0	0
T19	2526	2463	0	0
T20	5691	5628	0	0
T21	1333	1238	0	0
T22	1860	1767	0	0
T23	1578	1489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	184847208	0	0
T1	1057	994	0	0
T2	2200	2051	0	0
T3	3250	3192	0	0
T4	7434	7172	0	0
T8	3371	3278	0	0
T19	2526	2463	0	0
T20	5691	5628	0	0
T21	1333	1238	0	0
T22	1860	1767	0	0
T23	1578	1489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	184847208	0	0
T1	1057	994	0	0
T2	2200	2051	0	0
T3	3250	3192	0	0
T4	7434	7172	0	0
T8	3371	3278	0	0
T19	2526	2463	0	0
T20	5691	5628	0	0
T21	1333	1238	0	0
T22	1860	1767	0	0
T23	1578	1489	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	184866443	310308	0	0
T3	3250	1781	0	0
T4	7434	0	0	0
T5	0	474	0	0
T6	0	1666	0	0
T8	3371	906	0	0
T9	0	857	0	0
T11	3497	1313	0	0
T17	0	6596	0	0
T19	2526	0	0	0
T20	5691	0	0	0
T21	1333	0	0	0
T22	1860	0	0	0
T23	1578	0	0	0
T28	0	400	0	0
T34	0	109	0	0
T64	1023	0	0	0
T65	0	138	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T79,T80,T81
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T8,T11

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T35,T36,T37
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T11

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T31,T38,T82
1	0	1	Covered	T3,T8,T11
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T11
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	184687718	261678	0	0
DepthKnown_A	185001714	184847208	0	0
RvalidKnown_A	185001714	184847208	0	0
WreadyKnown_A	185001714	184847208	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	184866443	301005	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	184687718	261678	0	0
T3	3250	1605	0	0
T4	7434	0	0	0
T5	0	33	0	0
T6	0	57	0	0
T8	3371	889	0	0
T9	0	770	0	0
T11	3497	1321	0	0
T17	0	6589	0	0
T19	2526	0	0	0
T20	5691	0	0	0
T21	1333	0	0	0
T22	1860	0	0	0
T23	1578	0	0	0
T28	0	382	0	0
T29	0	294	0	0
T30	0	241	0	0
T64	1023	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	184847208	0	0
T1	1057	994	0	0
T2	2200	2051	0	0
T3	3250	3192	0	0
T4	7434	7172	0	0
T8	3371	3278	0	0
T19	2526	2463	0	0
T20	5691	5628	0	0
T21	1333	1238	0	0
T22	1860	1767	0	0
T23	1578	1489	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	184847208	0	0
T1	1057	994	0	0
T2	2200	2051	0	0
T3	3250	3192	0	0
T4	7434	7172	0	0
T8	3371	3278	0	0
T19	2526	2463	0	0
T20	5691	5628	0	0
T21	1333	1238	0	0
T22	1860	1767	0	0
T23	1578	1489	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185001714	184847208	0	0
T1	1057	994	0	0
T2	2200	2051	0	0
T3	3250	3192	0	0
T4	7434	7172	0	0
T8	3371	3278	0	0
T19	2526	2463	0	0
T20	5691	5628	0	0
T21	1333	1238	0	0
T22	1860	1767	0	0
T23	1578	1489	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	184866443	301005	0	0
T3	3250	1605	0	0
T4	7434	0	0	0
T5	0	446	0	0
T6	0	1574	0	0
T8	3371	889	0	0
T9	0	770	0	0
T11	3497	1321	0	0
T17	0	6589	0	0
T19	2526	0	0	0
T20	5691	0	0	0
T21	1333	0	0	0
T22	1860	0	0	0
T23	1578	0	0	0
T28	0	382	0	0
T34	0	111	0	0
T64	1023	0	0	0
T65	0	140	0	0