Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cfg_cg

Group : tb.dut.u_edn_cov_if::edn_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : edn_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance edn_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	21	0	21	100.00

Variables for Group Instance edn_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mode	3	0	3	100.00	100	1	1	0
cp_num_boot_reqs	2	0	2	100.00	100	1	1	0
cp_num_endpoints	7	0	7	100.00	100	1	1	8

Crosses for Group Instance edn_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_num_endpoints_mode	21	0	21	100.00	100	1	1	0

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Excluded/Illegal bins

NAME	COUNT	STATUS
both	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
boot_req_mode	134	1			T18	1		T20	1		T21	1
auto_req_mode	146	1			T2	1		T3	1		T9	1
sw_mode	2808	1			T1	1		T22	1		T70	1

---

Summary for Variable cp_num_boot_reqs

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

295

1

T3

1

T9

1

T18

1

single

103

1

T2

1

T73

1

T40

1

---

Summary for Variable cp_num_endpoints

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded
[auto[0]]	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	1315	1			T1	1		T2	1		T3	1
auto[2]	71	1			T70	1		T17	1		T74	1
auto[3]	145	1			T18	1		T203	3		T244	1
auto[4]	37	1			T268	17		T246	1		T269	1
auto[5]	138	1			T76	1		T81	1		T209	9
auto[6]	223	1			T36	36		T48	1		T189	83
auto[7]	1159	1			T19	1		T10	1		T21	1

---

Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	21	0	21	100.00

Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins

cp_num_endpoints	cp_mode	COUNT	STATUS
[auto[0]]	[boot_req_mode , auto_req_mode , sw_mode]	--	Excluded	(3 bins)

Covered bins

cp_num_endpoints	cp_mode	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[1]	boot_req_mode	80	1			T20	1		T59	1		T73	1
auto[1]	auto_req_mode	87	1			T2	1		T3	1		T9	1
auto[1]	sw_mode	1148	1			T1	1		T22	1		T5	8
auto[2]	boot_req_mode	3	1			T270	1		T271	1		T272	1
auto[2]	auto_req_mode	3	1			T17	1		T74	1		T273	1
auto[2]	sw_mode	65	1			T70	1		T216	1		T274	61
auto[3]	boot_req_mode	4	1			T18	1		T244	1		T275	1
auto[3]	auto_req_mode	6	1			T276	1		T277	1		T278	1
auto[3]	sw_mode	135	1			T203	3		T279	1		T280	1
auto[4]	boot_req_mode	2	1			T269	1		T281	1		-	-
auto[4]	auto_req_mode	3	1			T282	1		T283	1		T284	1
auto[4]	sw_mode	32	1			T268	17		T246	1		T285	1
auto[5]	boot_req_mode	2	1			T76	1		T286	1		-	-
auto[5]	auto_req_mode	3	1			T81	1		T213	1		T287	1
auto[5]	sw_mode	133	1			T209	9		T192	45		T288	52
auto[6]	boot_req_mode	3	1			T48	1		T289	1		T290	1
auto[6]	auto_req_mode	3	1			T291	1		T292	1		T293	1
auto[6]	sw_mode	217	1			T36	36		T189	83		T207	13
auto[7]	boot_req_mode	40	1			T21	1		T75	1		T79	1
auto[7]	auto_req_mode	41	1			T19	1		T10	1		T43	1
auto[7]	sw_mode	1078	1			T39	1		T40	1		T65	1