Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	629697	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4968705

1

T1

8

T2

62

T3

56

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1489017	1			T1	21		T2	50		T3	36
values[0x0]	1898720	1			T1	2		T2	38		T3	34
values[0x1]	2210665	1			T1	6		T2	25		T3	23

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	313470	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5284932

1

T1

16

T2

76

T3

71

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	20747	1			T70	2		T5	3		T14	1
valid_sources[0x01]	22401	1			T10	55		T5	2		T40	1
valid_sources[0x02]	22167	1			T5	2		T39	1		T14	2
valid_sources[0x03]	20308	1			T5	2		T63	1		T36	140
valid_sources[0x04]	21594	1			T70	5		T5	3		T39	1
valid_sources[0x05]	21707	1			T2	3		T22	2		T5	3
valid_sources[0x06]	21752	1			T50	2		T5	3		T26	2
valid_sources[0x07]	23329	1			T50	5		T4	2		T5	1
valid_sources[0x08]	22697	1			T5	8		T40	2		T64	4
valid_sources[0x09]	21154	1			T5	3		T14	1		T36	279
valid_sources[0x0a]	21310	1			T5	3		T14	2		T63	1
valid_sources[0x0b]	21489	1			T70	1		T4	1		T26	1
valid_sources[0x0c]	21457	1			T5	5		T63	2		T36	394
valid_sources[0x0d]	22414	1			T22	1		T5	1		T14	2
valid_sources[0x0e]	21641	1			T4	1		T5	4		T26	3
valid_sources[0x0f]	21390	1			T70	1		T4	2		T5	1
valid_sources[0x10]	21413	1			T70	2		T5	7		T14	2
valid_sources[0x11]	21018	1			T5	8		T26	2		T40	3
valid_sources[0x12]	20654	1			T5	5		T39	1		T26	3
valid_sources[0x13]	23798	1			T70	1		T5	2		T63	1
valid_sources[0x14]	23919	1			T5	1		T39	2		T60	3
valid_sources[0x15]	23614	1			T22	1		T4	1		T5	4
valid_sources[0x16]	23200	1			T22	1		T5	6		T58	1
valid_sources[0x17]	22382	1			T5	3		T39	1		T36	228
valid_sources[0x18]	21713	1			T5	2		T14	3		T63	1
valid_sources[0x19]	20882	1			T22	1		T5	2		T14	1
valid_sources[0x1a]	24331	1			T5	3		T60	4		T26	1
valid_sources[0x1b]	22071	1			T70	2		T39	2		T40	1
valid_sources[0x1c]	22329	1			T5	2		T60	7		T31	1
valid_sources[0x1d]	21432	1			T70	1		T5	7		T40	1
valid_sources[0x1e]	20204	1			T22	1		T5	2		T60	5
valid_sources[0x1f]	21146	1			T22	1		T70	1		T5	3
valid_sources[0x20]	20297	1			T70	3		T5	2		T39	2
valid_sources[0x21]	22061	1			T2	3		T5	5		T39	1
valid_sources[0x22]	21254	1			T2	4		T22	2		T70	1
valid_sources[0x23]	24115	1			T22	1		T4	1		T5	2
valid_sources[0x24]	21331	1			T2	1		T4	1		T5	5
valid_sources[0x25]	24430	1			T5	1		T39	1		T58	1
valid_sources[0x26]	21797	1			T22	3		T5	2		T23	5
valid_sources[0x27]	21124	1			T5	3		T40	1		T14	1
valid_sources[0x28]	22553	1			T70	2		T5	5		T60	2
valid_sources[0x29]	21415	1			T5	1		T36	266		T37	124
valid_sources[0x2a]	21391	1			T70	1		T5	6		T36	209
valid_sources[0x2b]	21689	1			T4	1		T5	2		T14	1
valid_sources[0x2c]	21839	1			T22	1		T70	1		T5	8
valid_sources[0x2d]	21740	1			T5	5		T63	1		T36	324
valid_sources[0x2e]	21770	1			T4	2		T5	3		T39	1
valid_sources[0x2f]	23071	1			T5	2		T58	1		T40	2
valid_sources[0x30]	19699	1			T5	4		T39	2		T40	1
valid_sources[0x31]	22343	1			T5	5		T40	1		T46	5
valid_sources[0x32]	21625	1			T70	7		T5	3		T63	5
valid_sources[0x33]	22422	1			T2	4		T70	3		T4	1
valid_sources[0x34]	21595	1			T22	1		T70	1		T4	3
valid_sources[0x35]	21200	1			T2	1		T70	1		T5	2
valid_sources[0x36]	22686	1			T5	5		T14	8		T36	315
valid_sources[0x37]	21647	1			T70	2		T5	2		T39	2
valid_sources[0x38]	22932	1			T70	1		T5	5		T36	315
valid_sources[0x39]	20861	1			T70	4		T50	2		T39	1
valid_sources[0x3a]	22008	1			T70	2		T5	4		T39	1
valid_sources[0x3b]	23086	1			T70	1		T5	1		T39	1
valid_sources[0x3c]	20324	1			T1	1		T5	1		T26	1
valid_sources[0x3d]	23080	1			T5	3		T26	1		T63	1
valid_sources[0x3e]	20922	1			T70	2		T5	4		T39	1
valid_sources[0x3f]	20601	1			T2	6		T50	2		T5	4
valid_sources[0x40]	23567	1			T5	2		T39	1		T40	1
valid_sources[0x41]	22817	1			T22	2		T70	2		T50	10
valid_sources[0x42]	20523	1			T4	1		T5	2		T40	1
valid_sources[0x43]	21872	1			T5	6		T14	3		T36	373
valid_sources[0x44]	21956	1			T5	5		T40	2		T14	6
valid_sources[0x45]	21254	1			T1	1		T70	1		T5	4
valid_sources[0x46]	21272	1			T70	6		T5	6		T39	1
valid_sources[0x47]	21168	1			T5	3		T36	151		T37	88
valid_sources[0x48]	21962	1			T70	5		T5	4		T36	315
valid_sources[0x49]	23438	1			T70	1		T5	4		T13	5
valid_sources[0x4a]	21908	1			T5	2		T39	2		T60	12
valid_sources[0x4b]	23059	1			T4	1		T5	4		T39	1
valid_sources[0x4c]	21083	1			T5	6		T36	240		T37	60
valid_sources[0x4d]	21358	1			T70	1		T5	1		T14	1
valid_sources[0x4e]	20792	1			T5	4		T39	1		T40	1
valid_sources[0x4f]	21894	1			T1	1		T4	1		T5	3
valid_sources[0x50]	21802	1			T22	1		T5	3		T14	2
valid_sources[0x51]	22125	1			T2	2		T5	6		T39	2
valid_sources[0x52]	20441	1			T4	1		T5	5		T39	2
valid_sources[0x53]	21948	1			T70	1		T5	6		T40	1
valid_sources[0x54]	21293	1			T4	1		T5	1		T39	1
valid_sources[0x55]	21930	1			T4	1		T5	3		T40	1
valid_sources[0x56]	21750	1			T22	3		T5	3		T26	1
valid_sources[0x57]	21942	1			T22	1		T5	1		T26	1
valid_sources[0x58]	20590	1			T5	4		T39	1		T13	2
valid_sources[0x59]	22076	1			T70	3		T5	5		T39	2
valid_sources[0x5a]	21577	1			T1	1		T22	1		T5	3
valid_sources[0x5b]	24257	1			T22	2		T4	1		T5	5
valid_sources[0x5c]	21357	1			T5	3		T14	1		T31	4
valid_sources[0x5d]	21613	1			T2	4		T70	3		T4	1
valid_sources[0x5e]	21501	1			T2	7		T70	1		T5	7
valid_sources[0x5f]	21802	1			T5	2		T26	1		T63	1
valid_sources[0x60]	22652	1			T70	1		T5	2		T26	1
valid_sources[0x61]	22638	1			T22	1		T70	1		T5	1
valid_sources[0x62]	21583	1			T2	6		T70	2		T5	2
valid_sources[0x63]	23545	1			T20	4		T22	2		T70	1
valid_sources[0x64]	22462	1			T70	5		T5	6		T39	1
valid_sources[0x65]	21716	1			T19	88		T5	4		T39	1
valid_sources[0x66]	23211	1			T22	1		T5	5		T39	1
valid_sources[0x67]	21915	1			T70	3		T4	2		T5	4
valid_sources[0x68]	22662	1			T5	1		T26	1		T36	309
valid_sources[0x69]	21862	1			T2	1		T5	4		T6	19
valid_sources[0x6a]	21376	1			T1	1		T22	1		T4	1
valid_sources[0x6b]	20742	1			T5	6		T58	2		T40	1
valid_sources[0x6c]	22197	1			T70	1		T5	6		T39	1
valid_sources[0x6d]	21318	1			T22	1		T70	5		T5	5
valid_sources[0x6e]	21603	1			T22	1		T5	4		T40	1
valid_sources[0x6f]	21574	1			T5	3		T40	1		T14	6
valid_sources[0x70]	21770	1			T4	1		T5	3		T31	1
valid_sources[0x71]	22351	1			T5	2		T36	199		T37	1136
valid_sources[0x72]	22487	1			T70	3		T4	2		T5	2
valid_sources[0x73]	23788	1			T5	4		T26	1		T40	3
valid_sources[0x74]	22400	1			T18	69		T70	1		T50	3
valid_sources[0x75]	23693	1			T70	3		T5	3		T14	3
valid_sources[0x76]	21502	1			T70	1		T5	1		T40	1
valid_sources[0x77]	22370	1			T22	1		T5	5		T39	1
valid_sources[0x78]	23147	1			T5	4		T14	2		T63	1
valid_sources[0x79]	22186	1			T2	9		T70	3		T5	2
valid_sources[0x7a]	20960	1			T22	1		T70	2		T5	6
valid_sources[0x7b]	22458	1			T70	1		T4	2		T5	6
valid_sources[0x7c]	21703	1			T5	7		T39	1		T14	4
valid_sources[0x7d]	21628	1			T5	3		T14	1		T31	1
valid_sources[0x7e]	21881	1			T4	1		T5	4		T40	1
valid_sources[0x7f]	21254	1			T4	2		T5	4		T39	2
valid_sources[0x80]	22318	1			T1	1		T2	3		T22	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1252293

1

T1

4

T2

2

T3

3

values[0x0]

all_enables

biggest_size

1858490

1

T2

36

T3

34

T9

33

values[0x1]

all_enables

biggest_size

1857922

1

T1

4

T2

24

T3

19