Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
65.62	65.62	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	65.62	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
65.62	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	22	30	57.69

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	22	30	57.69	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2652	1			T2	3		T3	4		T18	2
non_zero_bins[1]	1759	1			T2	4		T3	1		T9	5
zero	8235	1			T1	3		T2	1		T18	5

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	467	1			T5	2		T52	2		T36	3
uni	3484	1			T1	1		T2	1		T18	2
gen	3866	1			T1	1		T2	4		T3	2
res	830	1			T2	2		T3	2		T9	2
ins	3999	1			T1	1		T2	1		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8519

1

T1

3

T2

4

T3

2

mubi_true

4127

1

T2

4

T3

3

T9

4

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

35

1

T27

1

T28

1

T49

1

pass

12611

1

T1

3

T2

8

T3

5

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	22	30	57.69	22
Automatically Generated Cross Bins	52	22	30	57.69	22
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res , ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	12

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res , ins]	[zero]	[fail]	[mubi_true]	--	--	3

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	109	1			T37	4		T38	2		T148	3
upd	non_zero_bins[0]	pass	mubi_true	109	1			T5	1		T37	2		T38	2
upd	non_zero_bins[1]	pass	mubi_false	76	1			T37	5		T38	3		T75	1
upd	non_zero_bins[1]	pass	mubi_true	82	1			T5	1		T52	1		T36	2
upd	zero	pass	mubi_false	42	1			T52	1		T38	1		T148	1
upd	zero	pass	mubi_true	49	1			T36	1		T37	2		T191	1
uni	zero	fail	mubi_false	6	1			T145	1		T146	1		T147	1
uni	zero	pass	mubi_false	2540	1			T1	1		T2	1		T18	2
uni	zero	pass	mubi_true	938	1			T5	5		T149	1		T65	1
gen	non_zero_bins[0]	pass	mubi_false	482	1			T2	1		T3	2		T18	1
gen	non_zero_bins[0]	pass	mubi_true	504	1			T5	2		T40	1		T63	1
gen	non_zero_bins[1]	pass	mubi_false	337	1			T70	1		T5	1		T52	1
gen	non_zero_bins[1]	pass	mubi_true	301	1			T2	3		T9	2		T5	2
gen	zero	fail	mubi_false	19	1			T27	1		T49	1		T78	1
gen	zero	pass	mubi_false	1754	1			T1	1		T19	3		T5	2
gen	zero	pass	mubi_true	469	1			T18	1		T10	1		T20	1
res	non_zero_bins[0]	pass	mubi_false	215	1			T2	2		T52	1		T36	1
res	non_zero_bins[0]	pass	mubi_true	193	1			T3	2		T22	1		T60	1
res	non_zero_bins[1]	pass	mubi_false	129	1			T52	1		T36	2		T37	1
res	non_zero_bins[1]	pass	mubi_true	118	1			T9	2		T21	1		T36	1
res	zero	fail	mubi_false	4	1			T185	1		T240	1		T241	1
res	zero	pass	mubi_false	91	1			T18	1		T19	2		T36	2
res	zero	pass	mubi_true	80	1			T10	2		T41	4		T36	2
ins	non_zero_bins[0]	pass	mubi_false	522	1			T59	1		T52	2		T36	6
ins	non_zero_bins[0]	pass	mubi_true	518	1			T18	1		T5	3		T59	1
ins	non_zero_bins[1]	pass	mubi_false	354	1			T9	1		T52	3		T36	2
ins	non_zero_bins[1]	pass	mubi_true	362	1			T2	1		T3	1		T19	1
ins	zero	fail	mubi_false	6	1			T28	1		T131	1		T242	1
ins	zero	pass	mubi_false	1833	1			T1	1		T21	1		T70	2
ins	zero	pass	mubi_true	404	1			T18	1		T10	1		T20	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded