Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.67	100.00	100.00		73.33	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	94.67	100.00	100.00		73.33	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.67	100.00	100.00		73.33	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.67	100.00	100.00		73.33	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		106	106	100.00
ALWAYS	42	3	3	100.00
CONT_ASSIGN	44	1	1	100.00
ALWAYS	47	102	102	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
42	3	3
44	1	1
47	1	1
48	1	1
49	1	1
50	1	1
51	1	1
52	1	1
53	1	1
54	1	1
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
61	1	1
63	1	1
64	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
77	1	1
78	1	1
81	1	1
82	1	1
			MISSING_ELSE
86	1	1
87	1	1
90	1	1
91	1	1
			MISSING_ELSE
95	1	1
98	1	1
99	1	1
			MISSING_ELSE
103	1	1
104	1	1
107	1	1
108	1	1
109	1	1
			MISSING_ELSE
114	1	1
115	1	1
116	1	1
			MISSING_ELSE
120	1	1
121	1	1
122	1	1
			MISSING_ELSE
126	1	1
127	1	1
128	1	1
			MISSING_ELSE
132	1	1
133	1	1
134	1	1
135	1	1
137	1	1
138	1	1
140	1	1
145	1	1
146	1	1
147	1	1
150	1	1
151	1	1
152	1	1
153	1	1
			MISSING_ELSE
157	1	1
158	1	1
159	1	1
162	1	1
163	1	1
164	1	1
165	1	1
			MISSING_ELSE
169	1	1
172	1	1
175	1	1
183	1	1
184	1	1
186	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
207	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	14	14	100.00
Logical	14	14	100.00
Non-Logical	0	0
Event	0	0

 LINE       63
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T13,T73
1	1	Covered	T18,T20,T21

 LINE       65
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T60,T41
1	1	Covered	T2,T3,T9

 LINE       183
 EXPRESSION (local_escalate_i || csrng_ack_err_i)
             --------1-------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
1	0	Covered	T4,T6,T13

 LINE       184
 EXPRESSION (local_escalate_i ? Error : RejectCsrngEntropy)
             --------1-------

-1-	Status	Tests
0	Covered	T26,T27,T28
1	Covered	T4,T6,T13

 LINE       197
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T6,T13

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	20	20	100.00	(Not included in score)
Transitions	75	55	73.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	153	Covered	T2,T3,T9
AutoCaptGenCnt	140	Covered	T2,T3,T9
AutoCaptReseedCnt	138	Covered	T2,T3,T9
AutoDispatch	122	Covered	T2,T3,T9
AutoFirstAckWait	116	Covered	T2,T3,T9
AutoLoadIns	68	Covered	T2,T3,T9
AutoSendGenCmd	147	Covered	T2,T3,T9
AutoSendReseedCmd	159	Covered	T2,T3,T9
BootDone	95	Covered	T18,T20,T21
BootGenAckWait	87	Covered	T18,T20,T21
BootInsAckWait	78	Covered	T18,T20,T21
BootLoadGen	82	Covered	T18,T20,T21
BootLoadIns	64	Covered	T18,T20,T21
BootLoadUni	99	Covered	T18,T21,T59
BootPulse	91	Covered	T18,T20,T21
BootUniAckWait	104	Covered	T18,T21,T59
Error	184	Covered	T4,T6,T13
Idle	109	Covered	T1,T2,T3
RejectCsrngEntropy	184	Covered	T26,T27,T28
SWPortMode	73	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	128	Covered	T2,T3,T9
AutoAckWait->Error	184	Covered	T7,T94,T95
AutoAckWait->Idle	207	Covered	T60,T41,T68
AutoAckWait->RejectCsrngEntropy	184	Covered	T49,T96,T97
AutoCaptGenCnt->AutoSendGenCmd	147	Covered	T2,T3,T9
AutoCaptGenCnt->Error	184	Covered	T98,T99
AutoCaptGenCnt->Idle	207	Covered	T60,T100,T101
AutoCaptGenCnt->RejectCsrngEntropy	184	Not Covered
AutoCaptReseedCnt->AutoSendReseedCmd	159	Covered	T2,T3,T9
AutoCaptReseedCnt->Error	184	Covered	T102,T103,T104
AutoCaptReseedCnt->Idle	207	Covered	T105,T106
AutoCaptReseedCnt->RejectCsrngEntropy	184	Not Covered
AutoDispatch->AutoCaptGenCnt	140	Covered	T2,T3,T9
AutoDispatch->AutoCaptReseedCnt	138	Covered	T2,T3,T9
AutoDispatch->Error	184	Not Covered
AutoDispatch->Idle	135	Covered	T2,T3,T9
AutoDispatch->RejectCsrngEntropy	184	Not Covered
AutoFirstAckWait->AutoDispatch	122	Covered	T2,T3,T9
AutoFirstAckWait->Error	184	Covered	T107,T108,T109
AutoFirstAckWait->Idle	207	Covered	T77,T110,T111
AutoFirstAckWait->RejectCsrngEntropy	184	Not Covered
AutoLoadIns->AutoFirstAckWait	116	Covered	T2,T3,T9
AutoLoadIns->Error	184	Covered	T4,T8,T112
AutoLoadIns->Idle	207	Covered	T4,T41,T7
AutoLoadIns->RejectCsrngEntropy	184	Not Covered
AutoSendGenCmd->AutoAckWait	153	Covered	T2,T3,T9
AutoSendGenCmd->Error	184	Covered	T113,T114,T115
AutoSendGenCmd->Idle	207	Covered	T116,T117,T118
AutoSendGenCmd->RejectCsrngEntropy	184	Not Covered
AutoSendReseedCmd->AutoAckWait	165	Covered	T2,T3,T9
AutoSendReseedCmd->Error	184	Covered	T119,T120,T121
AutoSendReseedCmd->Idle	207	Covered	T68,T83,T122
AutoSendReseedCmd->RejectCsrngEntropy	184	Not Covered
BootDone->BootLoadUni	99	Covered	T18,T21,T59
BootDone->Error	184	Covered	T56,T123,T124
BootDone->Idle	207	Covered	T46,T72,T84
BootDone->RejectCsrngEntropy	184	Not Covered
BootGenAckWait->BootPulse	91	Covered	T18,T20,T21
BootGenAckWait->Error	184	Covered	T125,T126,T127
BootGenAckWait->Idle	207	Covered	T6,T13,T128
BootGenAckWait->RejectCsrngEntropy	184	Covered	T26,T27,T78
BootInsAckWait->BootLoadGen	82	Covered	T18,T20,T21
BootInsAckWait->Error	184	Covered	T54,T129,T130
BootInsAckWait->Idle	207	Covered	T54,T56,T57
BootInsAckWait->RejectCsrngEntropy	184	Covered	T28,T131,T132
BootLoadGen->BootGenAckWait	87	Covered	T18,T20,T21
BootLoadGen->Error	184	Covered	T13,T128,T133
BootLoadGen->Idle	207	Covered	T47,T134,T135
BootLoadGen->RejectCsrngEntropy	184	Not Covered
BootLoadIns->BootInsAckWait	78	Covered	T18,T20,T21
BootLoadIns->Error	184	Covered	T57,T136,T137
BootLoadIns->Idle	207	Covered	T138,T139
BootLoadIns->RejectCsrngEntropy	184	Not Covered
BootLoadUni->BootUniAckWait	104	Covered	T18,T21,T59
BootLoadUni->Error	184	Not Covered
BootLoadUni->Idle	207	Not Covered
BootLoadUni->RejectCsrngEntropy	184	Not Covered
BootPulse->BootDone	95	Covered	T18,T20,T21
BootPulse->Error	184	Covered	T140,T141,T142
BootPulse->Idle	207	Covered	T73,T143,T144
BootPulse->RejectCsrngEntropy	184	Not Covered
BootUniAckWait->Error	184	Not Covered
BootUniAckWait->Idle	109	Covered	T18,T21,T59
BootUniAckWait->RejectCsrngEntropy	184	Covered	T145,T146,T147
Error->RejectCsrngEntropy	184	Not Covered
Idle->AutoLoadIns	68	Covered	T2,T3,T9
Idle->BootLoadIns	64	Covered	T18,T20,T21
Idle->Error	184	Covered	T14,T15,T16
Idle->RejectCsrngEntropy	184	Not Covered
Idle->SWPortMode	73	Covered	T1,T2,T3
RejectCsrngEntropy->Error	184	Not Covered
RejectCsrngEntropy->Idle	207	Covered	T26,T27,T28
SWPortMode->Error	184	Covered	T14,T71,T53
SWPortMode->Idle	207	Covered	T5,T14,T31
SWPortMode->RejectCsrngEntropy	184	Not Covered

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		41	41	100.00
IF	42	2	2	100.00
CASE	61	35	35	100.00
IF	183	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	42	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	61	case (state_q)
-2-:	63	if ((boot_req_mode_i && edn_enable_i))
-3-:	65	if ((auto_req_mode_i && edn_enable_i))
-4-:	69	if (edn_enable_i)
-5-:	81	if (csrng_cmd_ack_i)
-6-:	90	if (csrng_cmd_ack_i)
-7-:	98	if ((!boot_req_mode_i))
-8-:	107	if (csrng_cmd_ack_i)
-9-:	115	if (sw_cmd_req_load_i)
-10-:	121	if (csrng_cmd_ack_i)
-11-:	127	if (csrng_cmd_ack_i)
-12-:	133	if ((!auto_req_mode_i))
-13-:	137	if (max_reqs_cnt_zero_i)
-14-:	152	if (cmd_sent_i)
-15-:	164	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T20,T21
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T20,T21
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T20,T21
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Covered	T18,T20,T21
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T20,T21
BootGenAckWait	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T18,T20,T21
BootGenAckWait	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T18,T20,T21
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T20,T21
BootDone	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T18,T21,T59
BootDone	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T20,T6,T13
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T21,T59
BootUniAckWait	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T18,T21,T59
BootUniAckWait	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T18,T21,T59
AutoLoadIns	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T2,T3,T9
AutoLoadIns	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T2,T3,T9
AutoFirstAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T2,T3,T9
AutoFirstAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T2,T3,T9
AutoAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T2,T3,T9
AutoAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T2,T3,T9
AutoDispatch	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T2,T3,T9
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T2,T3,T9
AutoDispatch	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T2,T3,T9
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T2,T3,T9
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T2,T3,T9
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T9
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T9
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T9
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
RejectCsrngEntropy	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T26,T27,T28
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T6,T14,T72

	LineNo.	Expression
-1-:	183	if ((local_escalate_i || csrng_ack_err_i))
-2-:	184	(local_escalate_i) ? 
-3-:	197	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootInsAckWait, BootLoadGen, BootGenAckWait, BootLoadUni, BootUniAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode, RejectCsrngEntropy})))

Branches:

-1-	-2-	-3-	Status	Tests
1	1	-	Covered	T4,T6,T13
1	0	-	Covered	T26,T27,T28
0	-	1	Covered	T4,T6,T13
0	-	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	193689286	149746	0	0
FpvSecCmErrorStEscalate_A	193689286	150786	0	0
u_state_regs_A	193651711	193486100	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	149746	0	0
T4	1565	604	0	0
T5	16511	0	0	0
T6	758	308	0	0
T7	0	1070	0	0
T13	842	398	0	0
T14	0	8872	0	0
T23	1896	0	0	0
T39	5656	0	0	0
T51	1433	0	0	0
T53	0	588	0	0
T54	0	352	0	0
T58	1113	0	0	0
T59	3145	0	0	0
T60	2991	0	0	0
T71	0	762	0	0
T72	0	444	0	0
T88	0	605	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	150786	0	0
T4	1565	605	0	0
T5	16511	0	0	0
T6	758	309	0	0
T7	0	1071	0	0
T13	842	399	0	0
T14	0	9002	0	0
T23	1896	0	0	0
T39	5656	0	0	0
T51	1433	0	0	0
T53	0	589	0	0
T54	0	353	0	0
T58	1113	0	0	0
T59	3145	0	0	0
T60	2991	0	0	0
T71	0	763	0	0
T72	0	445	0	0
T88	0	606	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193651711	193486100	0	0
T1	1387	1318	0	0
T2	1998	1916	0	0
T3	3538	3471	0	0
T9	4212	4125	0	0
T10	2321	2227	0	0
T18	2905	2842	0	0
T19	1849	1759	0	0
T20	638	556	0	0
T21	3775	3676	0	0
T22	2122	2027	0	0